公开(公告)号：US20040134682A1

公开(公告)日：2004-07-15

申请号：US10751428

申请日：2004-01-06

Applicant: IBIDEN CO., LTD.

Inventor： Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

IPC: H05K001/00

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing. The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

Abstract translation: 本发明的目的是提供一种制造多层印刷电路板的方法，其能够同时通孔填充和形成导体电路，并且可以在基板和高密度布线上构造具有良好结晶度和均匀沉积的通孔 并且可以实现高可靠性的导体连接而不退火。 本发明涉及一种多层印刷电路板的制造方法，其特征在于，在形成有导体电路的基板上设置层间树脂绝缘层，在所述层间树脂绝缘层上形成用于形成通孔的开口，形成无电镀金属 层，在其上设置抗蚀剂，进行电镀，剥离抗蚀剂并蚀刻无电镀金属层以提供导体电路和通孔，其中使用所述无电镀金属层作为阴极间歇地进行电镀 以及在所述阳极和所述阴极之间的恒定电压下的电镀金属作为阳极。

公开(公告)号：US20040107569A1

公开(公告)日：2004-06-10

申请号：US10313932

申请日：2002-12-05

Inventor： John Guzek ,  Hamid Azimi ,  Dustin Wood

IPC: H01L029/00 ,  H01L023/48

CPC classification number: H01L23/49827 ,  H01L23/142 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/056 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Apparatus and methods are provided for a rigid metal core carrier substrate. The metal core increases the modulus of elasticity of the carrier substrate to greater than 20 GPa to better resist bending loads and stresses encountered during assembly, testing and consumer handling. The carrier substrate negates the need to provide external stiffening members resulting in a microelectronic package of reduced size and complexity. The coefficient of thermal expansion of the carrier substrate can be adapted to more closely match that of the microelectronic die, providing a device more resistant to thermally-induced stresses. In one embodiment of the method in accordance with the invention, a metal sheet having a thickness in the range including 200-500 nullm and a flexural modulus of elasticity of at least 20 GPa is laminated on both sides with dielectric and conductive materials using standard processing technologies to create a carrier substrate.

Abstract translation: 提供了用于刚性金属芯载体衬底的装置和方法。 金属芯将载体基板的弹性模量增加到大于20GPa，以更好地抵抗组装，测试和消费者处理期间遇到的弯曲载荷和应力。 载体基板不需要提供外部加强构件，导致尺寸减小和复杂度降低的微电子封装。 载体衬底的热膨胀系数可以适应于更紧密地匹配微电子管芯的热膨胀系数，从而提供对热诱导应力更耐受的器件。 在根据本发明的方法的一个实施方案中，使用标准处理的电介质和导电材料将具有200-500μm厚度的厚度和至少20GPa的挠曲弹性模量的金属片层压在两侧上 创造载体基板的技术。

公开(公告)号：US06731189B2

公开(公告)日：2004-05-04

申请号：US10185853

申请日：2002-06-27

Applicant: Angelo Puzella ,  Joseph M. Crowder ,  Patricia S. Dupuis ,  Michael C. Fallica

Inventor： Angelo Puzella ,  Joseph M. Crowder ,  Patricia S. Dupuis ,  Michael C. Fallica

IPC: H01L21768

CPC classification number: H01P3/085 ,  H01P3/088 ,  H05K1/0237 ,  H05K3/321 ,  H05K3/462 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10234 ,  H05K2203/061

Abstract: A multi-layer stripline assembly interconnection includes a first stripline sub-assembly having a first surface and a first plurality of vias disposed in the first surface adapted to receive a plurality of solid metal balls. The interconnection further includes a second stripline sub-assembly having a second plurality of vias disposed in the first surface of the second sub-assembly adapted to be aligned with the first plurality of vias. Reflowed solder is wetted to the second plurality of vias and to the corresponding plurality of solid metal balls.

Abstract translation: 多层带状线组合互连包括具有第一表面的第一带状线子组件和设置在第一表面中的适于容纳多个固体金属球的第一多个通孔。 互连还包括第二带状线子组件，其具有设置在第二子组件的第一表面中的适于与第一多个通孔对准的第二多个通孔。 回流焊料被润湿到第二多个通孔和对应的多个固体金属球。

公开(公告)号：US06730859B2

公开(公告)日：2004-05-04

申请号：US09817947

申请日：2001-03-27

Applicant: Shigetsugu Muramatsu ,  Kazunari Imai

Inventor： Shigetsugu Muramatsu ,  Kazunari Imai

IPC: H01R1204

CPC classification number: H05K3/3447 ,  H05K3/002 ,  H05K3/0032 ,  H05K3/0094 ,  H05K3/4602 ,  H05K2201/092 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2203/1394 ,  Y10T29/49139

Abstract: A substrate for mounting an electronic part or parts thereon, which comprises a core substrate and at least a set of insulation layer and patterned wiring line layer, which is formed on the insulation layer, at at least one side of the core substrate, the core substrate having holes, in each of which a lead pin of the electronic part to be mounted is to be inserted, and being provided with lands which surround the opening of the hole and to which the lead pin inserted in the hole is to be bonded, wherein the insulation layer or layers at at least one side of the core substrate has bores, which expose the land at their bottoms, and communicate with the hole. A method of manufacturing such a substrate is also disclosed.

Abstract translation: 一种用于安装其上的电子部件的基板，其包括在所述芯基板的至少一侧上形成在所述绝缘层上的芯基板和至少一组绝缘层和图案化布线线层，所述芯 具有孔的基板，其中每个要安装的电子部件的引脚插入，并且设置有围绕孔的开口的焊盘，插入孔中的引脚与引脚抵接， 其中所述芯基板的至少一侧的所述绝缘层或多个孔具有孔，其在其底部暴露所述焊盘并与所述孔连通。 还公开了制造这种基板的方法。

公开(公告)号：US20040074669A1

公开(公告)日：2004-04-22

申请号：US10310803

申请日：2002-12-06

Inventor： Mitsunori Nagashima ,  Tomoyoshi Hiei

IPC: H05K001/11

CPC classification number: H05K3/3405 ,  H05K1/113 ,  H05K3/3421 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/1028 ,  H05K2201/1034 ,  Y10T29/49165

Abstract: A circuit board comprises a board substrate including a substrate layer formed with a pad on an upper surface thereof, and a metal piece soldered on the pad. At least one through-hole including an internal wall formed with a conductive film is provided at a portion corresponding to the pad on the substrate layer. The through-hole is filled with a predetermined filler for closing at least an open mouth of the through-hole at the upper surface of the substrate layer. The pad is connected integrally with the conductive film on the internal wall of the through-hole.

Abstract translation: 一种电路板包括一个板基板，该基板包括一个在其上表面上形成有一个焊盘的基板层，以及一个焊接在焊盘上的金属片。 至少一个包括形成有导电膜的内壁的通孔设置在与衬底层上的衬垫相对应的部分。 填充有用于在基材层的上表面封闭通孔的至少一个开放口的预定填料。 衬垫与通孔内壁上的导电膜一体连接。

公开(公告)号：US06713792B2

公开(公告)日：2004-03-30

申请号：US10060563

申请日：2002-01-30

Applicant: Leendert J. van der Windt

Inventor： Leendert J. van der Windt

IPC: H01L2348

CPC classification number: H05K3/44 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0243 ,  H05K1/182 ,  H05K3/0047 ,  H05K3/0061 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/09618 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/175

Abstract: A method of manufacturing a printed circuit board through-hole connection includes forming a through-hole by removing material from the first side of the printed circuit board until the backing and then slightly into the first side of the backing providing a hole. Next, plating through the hole connecting the backing layer, ground layer, and signal layer. Now the plating of the signal layer is removed without removing the connection from the ground layer to the backing. Finally, the hole is filled from the first side of the printed circuit board. A method of manufacturing a MMIC printed circuit board through-hole connection includes forming a through-hole by removing material from the first side of the MMIC printed circuit board through the first signal layer, through the MMIC until the second signal layer, and then slightly into the top side of the second signal layer. Once the material is removed, an electrical connection is provided to the first signal layer, the MMIC and the second signal layer. A printed circuit board through-hole connection that includes an assembled layout of a printed circuit board and formed through holes by material removed from the first side of the printed circuit board up to the backing and then slightly into the top portion of the backing. It further includes plated through-holes that connect the backing, a ground layer and a signal layer, removed plating from the signal layer without the connection removed from the ground layer to the backing and filled through-holes from the first side with a non conductive filler.

Abstract translation: 制造印刷电路板通孔连接的方法包括通过从印刷电路板的第一侧去除材料形成通孔，直到背衬，然后略微进入背衬的第一侧，提供孔。 接下来，通过连接背衬层，接地层和信号层的孔进行电镀。 现在，消除信号层的电镀，而不需要从接地层到背衬的连接。 最后，从印刷电路板的第一侧填充孔。一种制造MMIC印刷电路板通孔连接的方法包括：通过从MMIC印刷电路板的第一面去除材料，形成通孔 第一个信号层，通过MMIC直到第二个信号层，然后稍微进入第二个信号层的顶端。 一旦材料被去除，就向第一信号层，MMIC和第二信号层提供电连接。一种印刷电路板通孔连接，其包括印刷电路板的组装布局并且通过被去除材料形成的孔 从印刷电路板的第一侧直到背衬，然后稍微进入背衬的顶部。 它还包括连接背衬，接地层和信号层的电镀通孔，从信号层移除镀层，而不将接地层从接地层移除到背衬，并从第一侧填充具有非导电性的通孔 填料。

公开(公告)号：US06703564B2

公开(公告)日：2004-03-09

申请号：US09812817

申请日：2001-03-21

Applicant: Shigeru Mori

Inventor： Shigeru Mori

IPC: H05K103

CPC classification number: H05K1/0271 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/0278 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959

Abstract: A printed wiring board is formed by a printed wiring substrate having a plurality of a wiring layer, and a thermal expansion buffering sheet having lower coefficient of thermal expansion than that of said printed wiring substrate, which is integrally laminated on a surface of the printed wiring substrate.

Abstract translation: 印刷布线板由具有多个布线层的印刷布线基板和热膨胀系数比所述印刷布线基板的热膨胀系数低的热膨胀缓冲片形成，该片材整体层压在印刷布线的表面上 基质。

公开(公告)号：US20040040744A1

公开(公告)日：2004-03-04

申请号：US10101211

申请日：2002-03-20

Inventor： Aneta D. Wyrzykowska ,  Luigi G. Difilippo ,  Herman Kwong

IPC: H05K007/08

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734 ,  Y10T29/49155

Abstract: A technique for reducing the number of layers in a multilayer circuit board is disclosed. The multilayer circuit board has a plurality of electrically conductive signal layers for routing electrical signals to and from at least one electronic component mounted on a surface of the multilayer circuit board. In one embodiment, the technique is realized by a method for reducing the number of layers in a multilayer circuit board, the multilayer circuit board having a plurality of electrically conductive signal layers for routing electrical signals to and from at least one electronic component mounted on a surface of the multilayer circuit board. The method comprises the steps of: forming a plurality of electrically conductive vias in the multilayer circuit board extending from the surface of the multilayer circuit board to at least one of the plurality of electrically conductive signal layers; arranging the surface such that a first set of two power/ground pins corresponds to first via and a second set of two power/ground pins corresponds to a second via positioned adjacent the first via, thereby creating a channel; and routing a first plurality of electrical signals through the channel on the first of the plurality of electrically conductive signal layers.

Abstract translation: 公开了一种用于减少多层电路板中的层数的技术。 多层电路板具有多个导电信号层，用于将电信号传送到安装在多层电路板的表面上的至少一个电子部件和/或从安装在多层电路板的表面上的至少一个电子部件。 在一个实施例中，该技术通过一种用于减少多层电路板中的层数的方法实现，该多层电路板具有多个用于将电信号路由至至少一个安装在 多层电路板的表面。 该方法包括以下步骤：在多层电路板中形成从多层电路板的表面延伸到多个导电信号层中的至少一个的多个导电通孔; 布置表面使得第一组两个电源/接地引脚对应于第一通孔，并且第二组两个电源/接地引脚对应于邻近第一通孔定位的第二通孔，从而产生通道; 以及通过所述多个导电信号层中的所述第一导电信号层上的所述沟道路由第一多个电信号。

公开(公告)号：US20040003941A1

公开(公告)日：2004-01-08

申请号：US10326079

申请日：2002-12-23

Inventor： Guy A. Duxbury ,  Herman Kwong ,  Aneta Wyrzykowska ,  Luigi G. Difilippo

IPC: H05K007/06

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734

Abstract: A technique for electrically interconnecting electrical signals between an electronic component and a multilayer signal routing device is disclosed. In one particular exemplary embodiment, the technique may be realized as an interconnect array for electrically interconnecting electrical signals between an electronic component and a multilayer signal routing device having a plurality of electrically conductive signal path layers. In such a case, the interconnect array comprises a plurality of electrically conductive contacts grouped into a plurality of arrangements of electrically conductive contacts, wherein each of the plurality of arrangements of electrically conductive contacts are separated from other adjacent ones of the plurality of arrangements of electrically conductive contacts by a channel that is correspondingly formed in the multilayer signal routing device such that an increased number of electrical signals may be routed therein on the plurality of electrically conductive signal path layers.

Abstract translation: 公开了一种用于电连接电子部件和多层信号路由装置之间的电信号的技术。 在一个特定的示例性实施例中，该技术可以被实现为用于电连接电子部件和具有多个导电信号路径层的多层信号路由装置之间的电信号的互连阵列。 在这种情况下，互连阵列包括分组成多个导电触头布置的多个导电触头，其中导电触头的多个布置中的每一个与多个电气布置的其它相邻布置分离 通过相应地形成在多层信号路由设备中的信道的导电接触，使得可以在多个导电信号路径层上路由增加数量的电信号。

公开(公告)号：US20040003494A1

公开(公告)日：2004-01-08

申请号：US10403550

申请日：2003-03-31

Inventor： Hiroshi Asami ,  Hidetoshi Kusano ,  Yuji Nishitani ,  Ken Orui

IPC: H05K001/02 ,  H05K001/11

CPC classification number: H05K3/4694 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/0023 ,  H05K3/205 ,  H05K3/4617 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/09536 ,  H05K2201/09881 ,  H05K2201/09972 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: The present invention provides a method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A second wiring substrate formed on a supporting sheet made of metal and an adhesive layer are partially stacked on a predetermined region of a first wiring substrate by using the supporting sheet. After the lamination of the second wiring substrate, the supporting sheet is finally etched and removed. The second wiring substrate is stacked only on the portion required to be multilayered on the first wiring substrate to thereby reduce the amount of the construction material of the second wiring substrate.

Abstract translation: 本发明提供一种制造多层布线基板的方法，其可以以细间距保持导体图案的尺寸稳定性，从材料选择的角度解决对工艺的限制，并且进一步降低制造成本，并且 多层布线基板。 形成在由金属制成的支撑片和粘合剂层上的第二布线基板通过使用支撑片部分堆叠在第一布线基板的预定区域上。 在第二布线基板的层叠之后，最后蚀刻并去除支撑片。 第二布线基板仅堆叠在第一布线基板上需要多层的部分上，从而减少第二布线基板的结构材料的量。