公开(公告)号：US20150360939A1

公开(公告)日：2015-12-17

申请号：US14832786

申请日：2015-08-21

Applicant: InvenSense, Inc.

Inventor： Cerina Zhang ,  Martin Lim ,  Jongwoo Shin ,  Joseph Seeger

IPC: B81C1/00

CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/0023 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00269 ,  B81C2201/0104 ,  B81C2201/0132 ,  B81C2203/0145 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0792

Abstract: Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.

Abstract translation: 半导体制造工艺包括提供第一衬底，其具有设置在图案化顶层金属层上方的第一钝化层，并且还具有设置在第一钝化层上的第二钝化层; 第二钝化层具有顶表面。 所述方法还包括在第二钝化层的第一部分中形成开口，并且开口暴露第一钝化层的表面的一部分。 所述方法还包括图案化第二钝化层和第一钝化层以暴露图案化顶层金属层的部分并将第二基板和第一基板彼此接合。 接合发生在至少第一钝化层的暴露部分经历脱气的温度范围内。

公开(公告)号：US20150353352A1

公开(公告)日：2015-12-10

申请号：US14829738

申请日：2015-08-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sang Kyun LEE ,  Yil Suk YANG

IPC: B81C1/00

CPC classification number: B81C1/00682 ,  B81B3/0051 ,  B81C1/0015 ,  B81C2201/0132 ,  B81C2201/053 ,  H01L41/094 ,  H01L41/1134 ,  H01L41/1136 ,  H01M6/40 ,  H01M10/052 ,  H01M10/0585 ,  H02N2/18 ,  H02N2/181 ,  H02N2/188 ,  H03H3/02 ,  H03H3/08 ,  Y02E60/122 ,  Y10T29/42 ,  Y10T29/43

Abstract: Provided is an apparatus for harvesting/storing piezoelectric energy, including: a substrate having a groove at a side thereon; a piezoelectric MEMS cantilever having an end fixed to the substrate and the other end floating above the groove, and configured to convert and store an external vibration into electric energy; and a mass formed at one end of the piezoelectric MEMS cantilever and configured to apply a vibration, and a manufacturing method thereof.

Abstract translation: 提供一种用于收集/存储压电能量的装置，包括：在其一侧具有凹槽的基板; 压电MEMS悬臂，其一端固定在基板上，另一端悬在凹槽上方，并构造成将外部振动转换并存储成电能; 以及形成在压电MEMS悬臂的一端并构造成施加振动的质量及其制造方法。

公开(公告)号：US20150338435A1

公开(公告)日：2015-11-26

申请号：US14818095

申请日：2015-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hua Chu ,  Chun-Wen Cheng

IPC: G01P15/125 ,  G01P15/08 ,  B81C1/00 ,  G01C19/5719 ,  B81B3/00

CPC classification number: B81B3/0059 ,  B81B3/0056 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0118 ,  B81C1/00158 ,  B81C1/00714 ,  B81C2201/0112 ,  B81C2201/0132 ,  G01C19/5719 ,  G01P15/0802 ,  G01P15/125

Abstract: Methods and apparatus for forming MEMS devices. An apparatus includes at least a portion of a semiconductor substrate having a first thickness and patterned to form a moveable mass; a moving sense electrode forming the first plate of a first capacitance; at least one anchor patterned from the semiconductor substrate and having a portion that forms the second plate of the first capacitance and spaced by a first gap from the first plate; a layer of semiconductor material of a second thickness patterned to form a first electrode forming a first plate of a second capacitance and further patterned to form a second electrode overlying the at least one anchor and forming a second plate spaced by a second gap that is less than the first gap; wherein a total capacitance is formed that is the sum of the first capacitance and the second capacitance. Methods are disclosed.

Abstract translation: 用于形成MEMS器件的方法和装置。 一种装置包括具有第一厚度的半导体衬底的至少一部分并被图案化以形成可移动质量块; 形成第一电容的第一板的移动感测电极; 所述至少一个锚定体从所述半导体衬底图案化并且具有形成所述第一电容的所述第二板的部分并与所述第一板间隔开第一间隙; 图案化的第二厚度的半导体材料层，以形成形成第二电容的第一板的第一电极，并进一步图案化以形成覆盖至少一个锚的第二电极，并形成间隔第二间隙的第二板，该第二间隙较小 比第一个差距; 其中形成的总电容是第一电容和第二电容之和。 公开了方法。

公开(公告)号：US20150232331A1

公开(公告)日：2015-08-20

申请号：US14624130

申请日：2015-02-17

Applicant: Robert Bosch GmbH

Inventor： Axel GROSSE ,  Heiko STAHL

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00595 ,  B81B7/0077 ,  B81B2203/06 ,  B81B2207/07 ,  B81C1/00571 ,  B81C2201/0132 ,  B81C2201/053

Abstract: A layer structure for a micromechanical component, having: a first layer, which is usable both for an electrical wiring of the component and as electrode of the component; and a second layer which is resistant to oxide etching and is disposed below the first layer, the second layer being formed essentially in one plane.

Abstract translation: 一种用于微机械部件的层结构，具有：第一层，其可用于部件的电线和部件的电极; 以及耐氧化物蚀刻的第二层，并且设置在第一层的下方，第二层基本上形成在一个平面中。

公开(公告)号：US20150187579A1

公开(公告)日：2015-07-02

申请号：US14642968

申请日：2015-03-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rueijer LIN ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

CPC classification number: B81C1/00158 ,  B81B7/008 ,  B81B2207/015 ,  B81B2207/096 ,  B81C1/00246 ,  B81C1/00333 ,  B81C1/00539 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/0127 ,  B81C2203/0742 ,  B81C2203/0778 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02247 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802

Abstract: A method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.

Abstract translation: 在半导体器件制造期间在形成互连的镶嵌工艺中形成氮化钛（TiN）硬掩模的方法，同时控制由TiN硬掩模承载的应力的类型和大小。 TiN硬掩模以多层结构形成，其中通过重复包括TiN和氯PECVD沉积以及N2 / H2等离子体气体处理的工艺循环来连续形成每个子层。 在其形成期间，通过控制TiN子层的数量和等离子体气体处理持续时间来控制由TiN硬掩模承载的应力，使得应力可以平衡在常规制备的TiN硬掩模上预期的预定外部应力 ，这导致沟槽侧壁变形，沟槽开口收缩和间隙填充问题。

公开(公告)号：US08987059B2

公开(公告)日：2015-03-24

申请号：US13571264

申请日：2012-08-09

Applicant: Kai-Chih Liang ,  Chia-Hua Chu ,  Te-Hao Lee ,  Jiou-Kang Lee ,  Chung-Hsien Lin

Inventor： Kai-Chih Liang ,  Chia-Hua Chu ,  Te-Hao Lee ,  Jiou-Kang Lee ,  Chung-Hsien Lin

IPC: H01L21/50 ,  B81C1/00

CPC classification number: B81C1/00515 ,  B81B7/0006 ,  B81B7/0077 ,  B81B2201/0235 ,  B81B2203/0315 ,  B81B2207/07 ,  B81B2207/095 ,  B81B2207/096 ,  B81C1/00293 ,  B81C1/00301 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/0145 ,  B81C2203/035 ,  H01L2224/11

Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.

Abstract translation: 微机电系统（MEMS）装置可以包括在第一基板上的MEMS结构。 MEMS结构包括可移动元件。 在第一衬底上沉积第一导电材料并蚀刻第二衬底中的沟槽。 用第二导电材料填充沟槽并在第二导电材料和第二衬底上沉积第三导电材料。 将第一基板和第二基板接合并使第二基板的背面变薄，从而在沟槽中露出第二导电材料。

公开(公告)号：US20150050746A1

公开(公告)日：2015-02-19

申请号：US14527039

申请日：2014-10-29

Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY

Inventor： Michael D. HENRY ,  Andrew P. HOMYK ,  Axel SCHERER ,  Thomas A. TOMBRELLO ,  Sameer WALAVALKAR

IPC: G01N1/40

CPC classification number: B81C1/00111 ,  B01J19/0046 ,  B01J2219/00504 ,  B01J2219/00664 ,  B81B1/006 ,  B81B2203/0361 ,  B81B2207/056 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0159 ,  G01N1/405 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3086 ,  Y10T436/25375

Abstract: Methods for fabricating of high aspect ratio probes and deforming micropillars and nanopillars are described. Use of polymers in deforming nanopillars and micropillars is also described.

Abstract translation: 描述了制造高纵横比探针和变形微柱和纳米柱的方法。 还描述了聚合物在变形纳米柱和微柱体中的使用。

公开(公告)号：US20140335301A1

公开(公告)日：2014-11-13

申请号：US14361683

申请日：2012-12-21

Applicant: Micronit Microfluidics B.V.

Inventor： Ronny Van 'T Oever ,  Marko Theodoor Blom ,  Jeroen Haneveld ,  Johannes Oonk ,  Marinus Bernardus Olde Riekerink ,  Peter Tijssen ,  Hendrik Jan Hildebrand Tigelaar ,  Jean-Noël Fehr ,  Jean-Christophe Roulet ,  Amitava Gupta

IPC: B81C1/00 ,  C23F1/02

CPC classification number: B81C1/00269 ,  B81B2201/058 ,  B81C3/001 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/019 ,  C23F1/02 ,  H01L21/50 ,  H01L23/10 ,  H01L2924/0002 ,  Y10T428/239 ,  H01L2924/00

Abstract: The invention relates to method for bonding at least two substrates, for example made from glass, silicon, ceramic, aluminum, or boron, by using an intermediate thin film metal layer for providing the bonding, said method comprising the following steps of: a) providing said two substrates; b) depositing said thin film metal layer on at least a part of a surface of a first substrate of the two substrates; c) bringing a surface of the second substrate into contact with said thin film metal layer on said surface of the first substrate such that a bonding between the second substrate and the thin film metal layer on the first substrate is provided; and d) at least locally strengthening the bonding between the second substrate and the thin film metal layer on the first substrate. The invention also relates to a device comprising two substrates, for example made from glass, silicon, ceramic, aluminum, or boron, and an intermediate thin film metal layer.

Abstract translation: 本发明涉及通过使用用于提供接合的中间薄膜金属层将至少两个基板（例如由玻璃，硅，陶瓷，铝或硼制成）接合的方法，所述方法包括以下步骤：a） 提供所述两个基板; b）将所述薄膜金属层沉积在所述两个基板的第一基板的表面的至少一部分上; c）使所述第二基板的表面与所述第一基板的所述表面上的所述薄膜金属层接触，从而提供所述第二基板和所述第一基板上的所述薄膜金属层之间的接合; 以及d）至少局部加强第一基板上的第二基板和薄膜金属层之间的接合。 本发明还涉及包括例如由玻璃，硅，陶瓷，铝或硼制成的两个基底和中间薄膜金属层的器件。

公开(公告)号：US20140291779A1

公开(公告)日：2014-10-02

申请号：US13851691

申请日：2013-03-27

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Martin Zgaga

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81B3/001 ,  B81B3/0051 ,  B81C1/00531 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

Abstract: A method includes a step of performing a time multiplexed etching process, wherein the last etching step of the time multiplexed etching process is of a first time duration. After performing the time multiplexed etching process, an etching step having a second time duration is performed, wherein the second time duration is greater than the first time duration.

Abstract translation: 一种方法包括执行时间复用蚀刻工艺的步骤，其中时间复用蚀刻工艺的最后一个蚀刻步骤是第一持续时间。 在执行时间复用蚀刻处理之后，执行具有第二持续时间的蚀刻步骤，其中第二持续时间大于第一持续时间。

公开(公告)号：US20140264644A1

公开(公告)日：2014-09-18

申请号：US13827928

申请日：2013-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ting-Hau Wu ,  Kuei-Sung Chang

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00801 ,  B81B3/0021 ,  B81B2201/0235 ,  B81B2207/012 ,  B81B2207/015 ,  B81C1/00587 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2203/036

Abstract: MEMS structures and methods utilizing a locker film are provided. In an embodiment a locker film is utilized to hold and support a moveable mass region during the release of the moveable mass region from a surrounding substrate. By providing additional support during the release of the moveable mass, the locker film can reduce the amount of undesired movement that can occur during the release of the moveable mass, and preventing undesired etching of the sidewalls of the moveable mass.

Abstract translation: 提供了使用更衣室膜的MEMS结构和方法。 在一个实施例中，使用更衣膜来在可移动质量区域与周围基底的释放期间保持和支撑可移动质量区域。 通过在可移动质量块的释放期间提供额外的支撑，更衣室膜可以减少在可移动质量块的释放期间可能发生的不期望的运动的量，并且防止可移动质量块的侧壁的不期望的蚀刻。