公开(公告)号：US20160308330A1

公开(公告)日：2016-10-20

申请号：US14782980

申请日：2014-04-10

Applicant: Florent LIFFRAN ,  Olivier RABOT

Inventor： Florent LIFFRAN ,  Olivier RABOT

IPC: H01S5/042 ,  H03K3/57

CPC classification number: H01S5/0428 ,  H03K3/57 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/10015 ,  H05K2201/10174 ,  H05K2201/10446 ,  H05K2201/10545 ,  Y02P70/611

Abstract: The invention concerns a device for controlling at least one diode 2, the control device comprising an electrical card 4 comprising a printed circuit 5 on which the following are mounted: a diode 2, a front component 7 and a storage capacitor 9 connected in such a way as to form a circuit loop 17 extending substantially in a thickness of the electrical card 4.

Abstract translation: 本发明涉及一种用于控制至少一个二极管2的装置，该控制装置包括一个电子卡4，该电子卡包括印刷电路5，其上安装有以下装置：二极管2，前部组件7和存储电容器9， 以形成基本上以电卡4的厚度延伸的电路回路17。

公开(公告)号：US09462675B2

公开(公告)日：2016-10-04

申请号：US12986447

申请日：2011-01-07

Applicant: Adam W. Gibson ,  Jeffrey Alan Poulsen

Inventor： Adam W. Gibson ,  Jeffrey Alan Poulsen

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0225 ,  H05K1/0216 ,  H05K1/0228 ,  H05K1/024 ,  H05K3/0044 ,  H05K2201/0792 ,  H05K2201/09063 ,  H05K2201/10189 ,  Y10T29/49124

Abstract: A method of improving electrical isolation between a first circuit and a second circuit sharing a common substrate having an effective dielectric constant greater than that of air. The first and second circuits are spaced apart and separated from one another by an intermediate portion of the substrate. The method includes removing a portion of the intermediate portion to replace the portion removed with air thereby reducing the effective dielectric constant of the intermediate portion. By reducing the effective dielectric constant of the intermediate portion, electrical isolation between the first and second circuits is improved thereby reducing crosstalk between the first and second circuits. In particular implementations, the method may be used to reduce alien crosstalk between adjacent communication outlets in a patch panel.

Abstract translation: 一种改善第一电路和共享具有大于空气的有效介电常数的公共衬底的第二电路之间的电隔离的方法。 第一和第二电路间隔开并且通过衬底的中间部分彼此分离。 该方法包括去除中间部分的一部分以取代用空气除去的部分，从而降低中间部分的有效介电常数。 通过降低中间部分的有效介电常数，改善第一和第二电路之间的电隔离，从而减少第一和第二电路之间的串扰。 在具体的实现中，该方法可以用于减少接线板中的相邻通信插座之间的外来串扰。

公开(公告)号：US20150364999A1

公开(公告)日：2015-12-17

申请号：US14739756

申请日：2015-06-15

Applicant: ROHM CO., LTD.

Inventor： Kiyoshi KONDO

IPC: H02M3/158

CPC classification number: H02M3/155 ,  H02M3/1588 ,  H05K1/0233 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/10674 ,  Y02B70/1466

Abstract: A semiconductor integrated circuit includes: a die pad region; a plurality of external lead pins arranged around the die pad region; and DC/DC converters arranged in corners on the die pad region.

Abstract translation: 半导体集成电路包括：管芯焊盘区域; 多个外部引线引脚布置在管芯焊盘区域周围; 以及布置在芯片焊盘区域上的角部的DC / DC转换器。

公开(公告)号：US09119334B2

公开(公告)日：2015-08-25

申请号：US13895675

申请日：2013-05-16

Applicant: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.

Inventor： Bhyrav M. Mutnury ,  Nam H. Pham ,  Terence Rodrigues

IPC: H01K3/10 ,  H05K3/42 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K3/42 ,  H05K1/024 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0792 ,  H05K2201/09063 ,  Y10T29/49165

Abstract: A circuit board includes layers, a pair of vias filled with a conductive material and extending through the layers, first and second pairs of conductive signal paths, and holes extending at least partially through the layers and located between the pair of vias. The first pair of conductive paths is connected to the pair of vias within a first layer; the second pair of conductive paths is connected to the pair of vias within a second layer. The pair of vias has a pair of via stubs defined between the second layer and a bottom layer. A differential signal is to be transmitted between the first and second pairs of conductive signal paths via the pair of vias. The holes have a lower dielectric constant than the layers to increase a resonant frequency of the pair of via stubs beyond the frequency of the differential signal.

Abstract translation: 电路板包括层，填充有导电材料并延伸通过层的一对通孔，第一和第二对导电信号路径，以及至少部分延伸通过层并且位于该对通孔之间的孔。 第一对导电路径连接到第一层内的一对通孔; 第二对导电路径连接到第二层内的一对通孔。 一对通孔具有限定在第二层和底层之间的一对通孔短截线。 差分信号将经由一对通孔在第一和第二对导电信号路径之间传输。 这些孔具有比层更低的介电常数，以增加一对通孔短路的谐振频率超过差分信号的频率。

公开(公告)号：US09035417B2

公开(公告)日：2015-05-19

申请号：US14142257

申请日：2013-12-27

Applicant: Efficient Power Conversion Corporation

Inventor： David Reusch ,  Johan Tjeerd Strydom

IPC: H01L23/528 ,  H01L23/538 ,  H01L27/13 ,  H01L27/06 ,  H02M7/00 ,  H01L23/498

CPC classification number: H01L27/0629 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/15192 ,  H02M7/003 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0265 ,  H05K2201/0792 ,  H05K2201/10166 ,  H01L2924/00

Abstract: A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.

Abstract translation: 高效的单面电路板布局设计，提供磁场自消除和降低的寄生电感，而与板厚无关。 低轮廓功率回路延伸穿过电路板顶层上的有源和无源器件，其中通孔将功率回路连接到板的内层中的返回路径。 通过将内层返回路径直接定位在顶层上的功率回路路径下方，可以降低功率回路部分功率回路在顶层上的磁效应。

公开(公告)号：US20140376201A1

公开(公告)日：2014-12-25

申请号：US13921550

申请日：2013-06-19

Applicant: Keithley Instruments, Inc.

Inventor： James A. Niemann ,  Gregory Sobolewski ,  Martin J. Rice ,  Wayne Goeke

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/46 ,  H05K3/30

CPC classification number: H05K1/0213 ,  H05K1/0225 ,  H05K1/0256 ,  H05K1/142 ,  H05K1/145 ,  H05K3/306 ,  H05K3/4038 ,  H05K3/4697 ,  H05K2201/0792 ,  H05K2201/09063 ,  H05K2201/093 ,  H05K2201/09618 ,  H05K2201/0969 ,  H05K2201/09981 ,  Y10T29/49139

Abstract: A device with low dielectric absorption includes a printed circuit board (PCB), a component connection area including a first conductor layered on a top surface of the component connection area and a second conductor layered on a bottom surface of the component connection area, an aperture surrounding the component connection area, a low-leakage component connecting the component connection area to the PCB across the aperture, and a guard composed of a third conductor at least substantially surrounding the aperture on a top surface of the PCB and a fourth conductor at least substantially surrounding the aperture on a bottom surface of the PCB.

Abstract translation: 具有低介电吸收率的器件包括印刷电路板（PCB），包括层叠在部件连接区域的顶表面上的第一导体的部件连接区域和层叠在部件连接区域的底表面上的第二导体， 围绕部件连接区域，将部件连接区域连接到穿过孔的PCB的低泄漏部件以及由至少基本上围绕PCB顶表面上的孔的第三导体组成的防护件和至少 基本上围绕PCB的底表面上的孔。

公开(公告)号：US08723374B2

公开(公告)日：2014-05-13

申请号：US13194383

申请日：2011-07-29

Applicant: Takeshi Kurihara ,  Keiichi Ichikawa

Inventor： Takeshi Kurihara ,  Keiichi Ichikawa

IPC: G05F3/06

CPC classification number: H02J50/10 ,  H01F38/14 ,  H02J5/005 ,  H02J7/025 ,  H02J50/12 ,  H02J50/70 ,  H05K1/0216 ,  H05K1/0265 ,  H05K1/115 ,  H05K2201/0792 ,  H05K2201/09627 ,  H05K2201/097 ,  H05K2201/0979 ,  H05K2201/1003 ,  H05K2201/10166

Abstract: The disclosure provides a non-contact power receiving apparatus including a conductive pattern in a second region of a substrate not covered by a magnetic sheet. The conductive pattern includes first and second electrodes provided in a first plane parallel to a surface of the substrate and arranged in a length direction of the conductive pattern. A third electrode is formed on a second plane parallel with the first plane. A first via hole connects superposed portions of the first and third electrodes to each other, and a second via hole connects superposed portions of the second and third electrodes to each other. As a result, loops of eddy currents generated in the conductive pattern can be made to be small, whereby eddy current loss can be reduced.

Abstract translation: 本公开提供一种非接触式电力接收装置，其包括在未被磁性片覆盖的基板的第二区域中的导电图案。 导电图案包括设置在与基板的表面平行的第一平面中并沿导电图案的长度方向布置的第一和第二电极。 第三电极形成在与第一平面平行的第二平面上。 第一通孔将第一和第三电极的叠置部彼此连接，第二通孔将第二电极和第三电极的叠置部彼此连接。 结果，可以使在导电图案中产生的涡流的回路小，从而可以减小涡流损耗。

公开(公告)号：US20130168143A1

公开(公告)日：2013-07-04

申请号：US13454680

申请日：2012-04-24

Applicant: Seung Wook Park ,  Mi Jin Park ,  Christian Romero ,  Young Do Kweon

Inventor： Seung Wook Park ,  Mi Jin Park ,  Christian Romero ,  Young Do Kweon

IPC: H05K1/09 ,  H05K1/02

CPC classification number: H05K1/025 ,  H05K1/0271 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/0792

Abstract: Disclosed herein is a circuit board including: an insulating material; a build-up layer formed on one surface of the insulating material, and including at least one circuit layer and at least one insulating layer; and a metal layer formed on the other surface of the insulating material and electrically disconnected from the circuit layer.

Abstract translation: 这里公开了一种电路板，包括：绝缘材料; 形成在所述绝缘材料的一个表面上并且包括至少一个电路层和至少一个绝缘层的堆积层; 以及形成在所述绝缘材料的另一个表面上并与所述电路层电连接的金属层。

公开(公告)号：US20120188729A1

公开(公告)日：2012-07-26

申请号：US13355008

申请日：2012-01-20

Applicant: Toshihiko NAKANO

Inventor： Toshihiko NAKANO

IPC: H05K1/00 ,  H05K3/10

CPC classification number: H05K1/0262 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/2518 ,  H01L2924/15311 ,  H05K1/0243 ,  H05K1/113 ,  H05K1/185 ,  H05K2201/0792 ,  Y10T29/49155

Abstract: A printed circuit board (PCB) according to an exemplary aspect of the present invention includes a plate-like member, a power supply circuit, a power supply line, and a ground line. The plate-like member has a surface on which a semiconductor device is mounted. The power supply circuit is embedded in the plate-like member in a region in which the semiconductor device is mounted, and outputs a power supply voltage and a ground voltage. The power supply line is formed in the plate-like member between the semiconductor device and the power supply circuit, and supplies the power supply voltage output from the power supply circuit to the semiconductor device. The ground line is formed in the plate-like member between the semiconductor device and the power supply circuit, and supplies the ground voltage output from the power supply circuit to the semiconductor device.

Abstract translation: 根据本发明的示例性方面的印刷电路板（PCB）包括板状构件，电源电路，电源线和接地线。 板状构件具有安装半导体器件的表面。 电源电路嵌入到安装有半导体器件的区域中的板状部件中，并输出电源电压和接地电压。 电源线形成在半导体器件和电源电路之间的板状构件中，并将从电源电路输出的电源电压提供给半导体器件。 接地线形成在半导体器件和电源电路之间的板状部件中，并将从电源电路输出的接地电压提供给半导体器件。

公开(公告)号：US08179695B2

公开(公告)日：2012-05-15

申请号：US12783478

申请日：2010-05-19

Applicant: Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

Inventor： Uei-Ming Jow ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Min-Lin Lee ,  Shinn-Juh Lai

IPC: H05K9/00

CPC classification number: H05K1/0218 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/09672

Abstract: A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Abstract translation: 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。