公开(公告)号：US10062672B2

公开(公告)日：2018-08-28

申请号：US15315256

申请日：2015-07-20

Applicant: LG Innotek Co., Ltd.

Inventor： Jung Oh Lee

IPC: H01L25/075 ,  H01L23/00 ,  H01L33/54 ,  H01L33/62 ,  H01L33/48 ,  H01L33/60 ,  A44C9/00 ,  A44C5/00 ,  B60R1/08 ,  B60R1/12

CPC classification number: H01L25/0753 ,  A44C5/0007 ,  A44C9/0053 ,  B60R1/088 ,  B60R1/12 ,  B60R1/1207 ,  B60R2001/1215 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L33/483 ,  H01L33/54 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/48105 ,  H01L2224/4814 ,  H01L2224/48228 ,  H01L2924/00014 ,  H05K1/189 ,  H05K3/284 ,  H05K2201/09227 ,  H05K2201/10106 ,  H05K2201/2054 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A light source module according to an embodiment includes: a flexible printed circuit board that has first and second pads; and a plurality of light emitting chips that are arranged on the first pads of the flexible printed circuit board, respectively, wherein the plurality of light emitting chips include a plurality of first arrays that are arranged in a first direction and second arrays that are arranged in a second direction that is different from the first direction, at least two of light emitting chips in each first array are connected to each other by the flexible printed circuit board, light emitting chips in each second array are electrically isolated from each other, the light source module further includes connection members, each of which is connected to at least one of the light emitting chips of the second array and a corresponding second pad of the flexible printed circuit board, and the connection members extend in the second direction.

公开(公告)号：US20180220524A1

公开(公告)日：2018-08-02

申请号：US15940863

申请日：2018-03-29

Applicant: QUALCOMM Incorporated

Inventor： Yokesh SUBRAMANIAN

IPC: H05K1/02 ,  G11C5/02 ,  H05K1/18

CPC classification number: H05K1/0213 ,  G11C5/025 ,  H05K1/0243 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/025 ,  H05K1/18 ,  H05K2201/09227 ,  H05K2201/09254

Abstract: A method for propagating a signal from an output driver on a PCB to a number of chips on the PCB. The signal is propagated from a first transmission line connected to the output driver, to a second transmission line connected to the first transmission line and a first chip, and to a third transmission line connected to the first transmission line and a second chip. The second transmission line has a length greater than or equal to 10 times the length of the first transmission line, and the third transmission line has a length greater than or equal to 10 times the length of the first transmission line. The lengths of the first transmission line, the second transmission line, and the third transmission line cause a reduction in reflections of the signal due to a change in impedance at a junction of the first, second, and third transmission lines.

公开(公告)号：US10006942B2

公开(公告)日：2018-06-26

申请号：US13892398

申请日：2013-05-13

Applicant: Intel IP Corporation

Inventor： Benjamin Orr ,  Harald Gossner

IPC: G01R31/02 ,  G01R1/073 ,  H05K1/11 ,  G01R31/00 ,  H05K1/14 ,  H05K1/02

CPC classification number: G01R1/07378 ,  G01R31/002 ,  H05K1/0268 ,  H05K1/11 ,  H05K1/144 ,  H05K2201/09227 ,  H05K2201/10378

Abstract: A board may include a first set of board contact pads arranged on a first side of the board, the pads configured to connect to circuit pads of a circuit under test, the positions of the pads matching to the positions of the circuit pads; a fan-out region on the first side of the board including fan-out contact pads configured to at least one of receive a test signal and provide a measurement signal; at least one contact pad connecting to at least one pad of the first set of board pads; and a second set of board contact pads on a second side of the board, the second set of board pads configured to connect to test board pads of a test board; positions of the pads matching to the positions of the test board pads; a pad connecting to a pad of the first set of board pads.

公开(公告)号：US20180108292A1

公开(公告)日：2018-04-19

申请号：US15527793

申请日：2016-07-01

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Pan XU

IPC: G09G3/20 ,  H05K1/14 ,  H01L27/12 ,  H05K1/18

CPC classification number: G09G3/2092 ,  G09G3/20 ,  G09G2300/0426 ,  H01L27/124 ,  H05K1/118 ,  H05K1/142 ,  H05K1/147 ,  H05K1/189 ,  H05K2201/049 ,  H05K2201/056 ,  H05K2201/09027 ,  H05K2201/09227 ,  H05K2201/10128 ,  H05K2201/10522

Abstract: A display device includes a display panel and a control circuit board configured to provide a driving signal to the display panel. The display panel includes a plurality of pixel structures of which pixel structures arranged in one row are connected to one gate line. Pixel structures arranged in one column are connected to one data line. The control circuit board includes a driving chip, an end portion of each of the gate lines and an end portion of each of the data lines are respectively provided with panel pins. The control circuit board is provided with circuit board pins to be electrically connected with the panel pins, and connecting lines through which pins of the control circuit board are connected to the circuit board pins. A spacing between adjacent circuit board pins is larger than a spacing between adjacent pins of the driving chip connected with the circuit board pins.

公开(公告)号：US09872397B2

公开(公告)日：2018-01-16

申请号：US13705747

申请日：2012-12-05

Applicant: INTEL CORPORATION

Inventor： Gary Brist

IPC: H05K3/34 ,  H01L23/498 ,  H05K1/11

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/111 ,  H05K2201/09227 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00

Abstract: The present disclosure provides techniques for creating a symmetrical ball grid array pattern for an integrated circuit package. The ball grid array includes a symmetrical pattern of circuit connection points, wherein the symmetrical pattern is derived from a base hexagonal pattern that is repeated in at least one or more sections of the ball grid array.

公开(公告)号：US09844133B2

公开(公告)日：2017-12-12

申请号：US15363579

申请日：2016-11-29

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshihiro Tomita ,  Koichi Hirano ,  Susumu Sawada ,  Koji Kawakita ,  Takashi Ichiryu ,  Masanori Nomura

IPC: H05K1/18 ,  H05K1/03

CPC classification number: H05K1/038 ,  H05K1/0283 ,  H05K1/0366 ,  H05K1/18 ,  H05K1/189 ,  H05K3/202 ,  H05K2201/0133 ,  H05K2201/029 ,  H05K2201/05 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/09945

Abstract: A flexible substrate is provided with: a stretchable sheet; a member located on the sheet; and a stretchable strip connected to the member, and located on the sheet. When the amount of extension of the sheet is equal to or less than a predetermined value, the sheet has a first elastic modulus, and when the amount of extension of the sheet exceeds the predetermined value, the sheet has a second elastic modulus that is greater than the first elastic modulus and greater than the elastic modulus of the strip.

公开(公告)号：US20170257957A1

公开(公告)日：2017-09-07

申请号：US15519579

申请日：2016-08-19

Applicant: BOE Technology Group Co., Ltd. ,  Chongqing BOE Optoelectronics Technology Co., Ltd.

Inventor： Zhuo Xu ,  Yajie Bai ,  Xiaoyuan Wang ,  Jaikwang Kim

IPC: H05K5/00 ,  H01R12/55 ,  H05K1/18 ,  H01R12/70

CPC classification number: H05K5/0017 ,  H01R12/55 ,  H01R12/7076 ,  H05K1/11 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/10128

Abstract: A printed circuit board, a display panel and a wiring method are provided by embodiments of the disclosure. The printed circuit board includes: a first multichannel circuit connecting terminal; a second multichannel circuit connecting terminal; and a plurality of connecting wires connecting a plurality of second channel connecting pins of the second multichannel circuit connecting terminal with a part of a first channel connecting pins of the first multichannel circuit connecting terminal in one-to-one correspondence, the rest of the first channel connecting pins being spare, where at least one of the plurality of connecting wires has a first portion, which is bent to extend through a spare region, on the printed circuit board, between the spare first channel connecting pins and the second multichannel circuit connecting terminal.

公开(公告)号：US20170176700A1

公开(公告)日：2017-06-22

申请号：US15394642

申请日：2016-12-29

Applicant: FINISAR CORPORATION

Inventor： Yan yang Zhao ,  Bernd Huebner ,  Tengda Du ,  Yuheng Lee

IPC: G02B6/42 ,  H05K1/02 ,  G01J1/04 ,  H05K1/11

CPC classification number: G02B6/4279 ,  G01J1/0425 ,  G02B6/4246 ,  G02B6/428 ,  G02B6/4292 ,  H05K1/0219 ,  H05K1/0224 ,  H05K1/0243 ,  H05K1/0274 ,  H05K1/0284 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/117 ,  H05K1/147 ,  H05K2201/09227 ,  H05K2201/09409 ,  H05K2201/0949 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/10121

Abstract: Multichannel RF Feedthroughs. In some examples, a multichannel RF feedthrough includes an internal portion and an external portion. The internal portion includes a top surface on which first and second sets of traces are formed. Each set of traces is configured as an electrical communication channel to carry electrical data signals. The external portion includes a bottom surface on which the first set of traces is formed and a top surface on which the second set of traces is formed. A set of vias connects the first set of traces between the top surface of the internal portion and the bottom surface of the external portion.

公开(公告)号：US20170164474A1

公开(公告)日：2017-06-08

申请号：US15367070

申请日：2016-12-01

Applicant: Samsung Display Co., Ltd.

Inventor： Byoungyong KIM ,  Inseok YEO ,  Euiyun JANG ,  Sangjun LEE ,  Jeongho HWANG

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/113 ,  H05K1/111 ,  H05K1/118 ,  H05K1/147 ,  H05K1/181 ,  H05K2201/05 ,  H05K2201/09227 ,  H05K2201/09409 ,  H05K2201/09481 ,  H05K2201/09709 ,  H05K2201/10128 ,  H05K2201/10545 ,  Y02P70/611

Abstract: Provided is a printed circuit board including a base substrate, first row pads, and second row pads. The base substrate has two sides, that can be adjacent, respectively extending in first and second directions. A plurality of pad group areas successively positioned along the first direction are defined on the base substrate. The first row pads are respectively disposed within the pad group areas and successively positioned along a third direction. The second row pads are respectively disposed within the pad group areas, successively positioned along the third direction, and spaced apart from the first row pads. Each of the second row pads is a predetermined distance from a corresponding one of the first row pads in the second direction.

公开(公告)号：US20170141065A1

公开(公告)日：2017-05-18

申请号：US15316640

申请日：2015-06-05

Applicant: SONY CORPORATION

Inventor： MAKOTO MURAI ,  YUJI TAKAOKA ,  KAZUKI SATO ,  HIROYUKI YAMADA

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/12 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0345 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/03912 ,  H01L2224/05166 ,  H01L2224/05173 ,  H01L2224/05647 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81012 ,  H01L2224/81065 ,  H01L2224/81075 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81385 ,  H01L2224/81444 ,  H01L2224/81815 ,  H01L2224/81893 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/8191 ,  H01L2224/81935 ,  H01L2224/81986 ,  H01L2224/831 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/83862 ,  H01L2224/83907 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09227 ,  H05K2201/09663 ,  H05K2201/0979 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/05442 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2224/814 ,  H01L2224/45099 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2221/68381 ,  H01L21/78 ,  H01L2224/03 ,  H01L2224/11

Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings. The plurality of first wirings connect the plurality of first electrodes, and the plurality of second wirings connect the plurality of second electrodes.