公开(公告)号：US5938455A

公开(公告)日：1999-08-17

申请号：US649735

申请日：1996-05-15

Applicant: Andrew Zachary Glovatsky ,  Michael George Todd ,  Peter Joseph Sinkunas ,  Myron Lemecha

Inventor： Andrew Zachary Glovatsky ,  Michael George Todd ,  Peter Joseph Sinkunas ,  Myron Lemecha

IPC: H01R31/08 ,  H05K1/00 ,  H05K1/11 ,  H05K3/32 ,  H05K3/36 ,  H05K3/40 ,  H05K3/42 ,  H01R9/09

CPC classification number: H01R12/58 ,  H01R12/523 ,  H05K1/119 ,  H05K3/326 ,  H05K3/368 ,  H01R31/08 ,  H05K1/0284 ,  H05K1/117 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09163 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10386 ,  H05K2201/10393 ,  H05K2201/1059 ,  H05K2201/209 ,  H05K2203/167 ,  H05K3/325 ,  H05K3/36 ,  H05K3/403 ,  H05K3/42

Abstract: A circuit board assembly is disclosed comprising a pair of three-dimensional substrates having integral, metallized connectors. The connector of the first substrate protrudes therefrom, while the connector of the second substrate is recessed therein. The geometries of the protruding connector and the recessed connector are different such that they deform when assembled to provide an electrical connection and a detachable physical connection. In one embodiment, the recessed connector has a parabolic cross-section and the protruding connector has a circular cross-section. A flexible molded edge connector for the circuit board assembly is also disclosed.

Abstract translation: 公开了一种电路板组件，其包括具有整体金属化连接器的一对三维基板。 第一基板的连接器从其突出，而第二基板的连接器凹入其中。 突出连接器和凹入连接器的几何形状不同，使得它们在组装时变形以提供电连接和可拆卸的物理连接。 在一个实施例中，凹入式连接器具有抛物面截面，并且突出连接器具有圆形横截面。 还公开了一种用于电路板组件的柔性成型边缘连接器。

公开(公告)号：US5918796A

公开(公告)日：1999-07-06

申请号：US800792

申请日：1997-02-14

Applicant: Shin Matsuda ,  Shingo Sato

Inventor： Shin Matsuda ,  Shingo Sato

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H05K3/3436 ,  H05K3/3484 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16195 ,  H05K2201/09472 ,  H05K2203/041 ,  H05K2203/043 ,  H05K3/3431 ,  H05K3/3478 ,  Y02P70/613

Abstract: A method of fabricating a package for housing a semiconductor element, comprising applying solder paste within plural depressions which are formed on at least one principal surface of an insulating substrate and have electrical connection pads, protruding the surface of the solder paste from the principal surface of the insulating substrate, mounting solder balls on the surface of the solder paste, and fusing the solder paste and the solder balls to produce unitary structures in order to form connection terminals with spherical protrusions.

Abstract translation: 一种制造用于容纳半导体元件的封装的方法，包括在多个凹陷中施加焊膏，所述多个凹陷形成在绝缘基板的至少一个主表面上并具有电连接焊盘，所述电连接焊盘从焊膏的主表面突出 绝缘基板，在焊膏表面上安装焊球，并且使锡膏和焊球融合以产生一体结构，以形成具有球形突起的连接端子。

公开(公告)号：US5898215A

公开(公告)日：1999-04-27

申请号：US766653

申请日：1996-12-16

Applicant: Dennis Brian Miller ,  Grace M. O'Malley ,  Brian R. Kemper

Inventor： Dennis Brian Miller ,  Grace M. O'Malley ,  Brian R. Kemper

IPC: G06K19/077 ,  H01L21/60 ,  H01L23/498 ,  H05K1/18 ,  H05K3/28 ,  H05K3/32 ,  H05K3/34 ,  H01L23/02 ,  H01L23/48

CPC classification number: H01L24/80 ,  G06K19/07745 ,  G06K19/0775 ,  H01L23/49855 ,  H05K3/321 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/183 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10689 ,  H05K2201/10931 ,  H05K3/28 ,  H05K3/3426

Abstract: A microelectronic assembly (10), such as a smart card, is formed by attaching a component subassembly (34) to a substrate (12). The substrate (12) includes a face (26) and defines a via (28) having a via opening (30) at the face (26). The substrate (12) further defines a component cavity (32) at the face (26) that is spaced apart from the via (28). An electrical element (14), such as a wound antenna, is disposed within the substrate (12) and includes a terminal (24) at the via (28). The component subassembly (34) is formed by mounting an integrated circuit component (16) onto a metallic lead (18). The integrated circuit component (16) is electrically connected to the metallic lead (18) by a wire lead (36). A protuberance (20) is connected to the metallic lead (18), preferably by forming a loop from a wire bond. A polymeric body (56) is formed about the component (16) and wire leads (36). The component subassembly (34) is superposed onto the substrate (12), and the component (16) is received in the component cavity (32). The metallic lead (18) is affixed to the face (26) and overlies the via opening (30). The protuberance (20) extends into the via (28) and contacts a conductive body (22) within the via (28). The conductive body (22) electrically connects the protuberance (20) and the terminal (24).

Abstract translation: 诸如智能卡的微电子组件（10）通过将部件子组件（34）附接到基板（12）而形成。 衬底（12）包括面（26）并且限定了在面（26）处具有通孔开口（30）的通孔（28）。 基板（12）还在与通孔（28）间隔开的面（26）处限定一个部件空腔（32）。 诸如伤口天线的电气元件（14）设置在衬底（12）内，并且在通孔（28）处包括端子（24）。 组件子组件（34）通过将集成电路部件（16）安装到金属引线（18）上而形成。 集成电路部件（16）通过引线（36）与金属引线（18）电连接。 突起（20）连接到金属引线（18），优选地通过从引线接合形成环。 围绕组件（16）和导线（36）形成聚合体（56）。 组件子组件（34）重叠在基板（12）上，并且部件（16）被容纳在部件空腔（32）中。 金属引线（18）固定在面（26）上并覆盖通孔（30）。 突起（20）延伸到通孔（28）中并与通孔（28）内的导电体（22）接触。 导电体（22）电连接突起（20）和端子（24）。

公开(公告)号：US5846853A

公开(公告)日：1998-12-08

申请号：US636915

申请日：1996-04-24

Applicant: Hideaki Otsuki ,  Toshio Kato ,  Yoko Gofuku ,  Fumio Matsukawa

Inventor： Hideaki Otsuki ,  Toshio Kato ,  Yoko Gofuku ,  Fumio Matsukawa

IPC: G02F1/13 ,  H01L21/56 ,  H01L21/60 ,  H05K3/00 ,  H05K3/10 ,  H05K3/28 ,  H05K3/30 ,  H05K3/32 ,  H01L21/288 ,  H01L21/58

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L24/73 ,  H01L24/83 ,  H01L24/90 ,  H05K3/321 ,  G02F1/13452 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/7525 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L24/11 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H05K2201/0108 ,  H05K2201/09472 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/0514 ,  H05K2203/0568 ,  H05K2203/1189 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/102 ,  H05K3/28 ,  H05K3/305

Abstract: A circuit substrate connection method for assuring to connect the semiconductor parts or sub-circuit substrate to a main circuit substrate such as liquid crystal display panel by avoiding a short between the electrodes on the same substrate. In the present invention, photosensitive resin including conductive particulates is painted on the transparent circuit substrate, and a light is radiated from the bottom of the main circuit substrate. As the electrode of the circuit substrate shields the light, the conductive particulates are removed together with the photosensitive resin other than on the electrode by developing the main circuit substrate. Further, in the present invention, the photosensitivity resin is painted on the transparent main circuit substrate, the photosensitivity resin on the electrode on the main circuit substrate are removed, the conductive particulates are filled in the removed portion, and thus only the conductive particulates are arranged only on the electrodes.

Abstract translation: 一种电路基板连接方法，用于通过避免在相同基板上的电极之间的短路来确保将半导体部件或子电路基板连接到诸如液晶显示面板的主电路基板。 在本发明中，在透明电路基板上涂布含有导电性微粒的感光性树脂，从主电路基板的底部照射光。 由于电路基板的电极屏蔽光，所以通过显影主电路基板，导电颗粒与除电极之外的感光树脂一起除去。 此外，在本发明中，在透明主电路基板上涂布感光性树脂，除去主电路基板上的电极上的光敏树脂，将导电性微粒填充在去除部分中，因此仅导电性微粒为 只布置在电极上。

公开(公告)号：US5844315A

公开(公告)日：1998-12-01

申请号：US621912

申请日：1996-03-26

Applicant: Cynthia M. Melton ,  George N. Demet ,  Iwona Turlik

Inventor： Cynthia M. Melton ,  George N. Demet ,  Iwona Turlik

IPC: H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495 ,  H05K3/34 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L21/568 ,  H01L23/3107 ,  H01L23/49517 ,  H05K3/3436 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/854 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18165 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10977 ,  Y02P70/613

Abstract: A microelectronic package (10) is formed by placing a lead frame (22) onto an adhesive polyimide tape (38). The lead frame (22) includes a plurality of metallic leads (16) and an opening. An integrated circuit die (12) is positioned onto the molding support (38) within the opening such that a non-active face (32) of the integrated circuit die (12) rests against the molding support (38). Wire leads (18) connect an active face (28) of the integrated circuit die (12) to the metallic leads (16). A plurality of metallic bumps (20) are attached to the metallic leads (16), and a polymeric precursor is dispensed. The precursor embeds the active face (28) of the integrated circuit die (12), the inner surface (19) of the metallic leads (16), the wire leads (18), and the metallic bumps (20). The microelectronic package (10) is then heated to cure the polymeric precursor to form a polymeric body (14). The microelectronic package (10) is then capable of being tested and subsequently attached to a printed circuit board (40) to form a low-profile microelectronic assembly (11).

Abstract translation: 通过将引线框架（22）放置在粘合聚酰亚胺胶带（38）上形成微电子封装（10）。 引线框架（22）包括多个金属引线（16）和开口。 集成电路模具（12）被定位在开口内的模制支撑件（38）上，使得集成电路模具（12）的非活动面（32）靠在模制支撑件（38）上。 导线（18）将集成电路管芯（12）的有源面（28）连接到金属引线（16）。 多个金属凸块（20）连接到金属引线（16）上，分配聚合物前体。 前体嵌入集成电路管芯（12）的有源面（28），金属引线（16）的内表面（19），引线引线（18）和金属凸块（20）。 然后加热微电子封装（10）以固化聚合物前体以形成聚合体（14）。 微电子封装（10）然后能够被测试并随后连接到印刷电路板（40）以形成低调微电子组件（11）。

公开(公告)号：US5805431A

公开(公告)日：1998-09-08

申请号：US588074

申请日：1996-01-17

Applicant: Shankar R. Joshi ,  Meta Rohde

Inventor： Shankar R. Joshi ,  Meta Rohde

IPC: H01F27/29 ,  H05K3/34 ,  H01F27/30 ,  H01F27/04

CPC classification number: H01F27/292 ,  H05K3/3442 ,  H05K2201/09472 ,  Y02P70/613 ,  Y10S439/931

Abstract: A surface mount package particularly suitable for transformers and other components having numerous windings of fragile, difficult to handle wire has a housing which includes openings along the lower edge, the housing being plated with an electrically conductive material on portions of the lower edge and in areas surrounding the opening. A component is held within the housing, and the leads of the component are disposed in the openings at a point above the lower edge of the housing, and the leads are electrically connected to the plating surrounding the openings and the plating at the flat portions of the lower edge. The plating on the flat portions of the lower edge can be at any suitable location, i.e., remote from or adjacent to the openings. Additional components can be stacked on the exterior of the housing, as connected to the plating surrounding the openings. Also, the walls and/or the top of the housing can be plated to provide for versatility in connecting the housed component, or any other components, on and around the housing. The plating on the housing may be connected to the plating surrounding the openings and the plating at the flat portions of the lower edge, or may entirely independent of the housed electronic component.

Abstract translation: 特别适用于具有易碎，难以处理的线的多个绕组的变压器和其它部件的表面安装封装具有壳体，该壳体包括沿着下边缘的开口，该壳体在下边缘的部分和区域中被电镀有导电材料 围绕开幕。 部件被保持在壳体内，并且部件的引线在壳体的下边缘上方的点处设置在开口中，并且引线电连接到围绕开口的电镀和在平坦部分的电镀 下边缘。 在下边缘的平坦部分上的电镀可以在任何合适的位置，即远离或邻近开口。 附加部件可以堆叠在外壳的外部，连接到围绕开口的电镀层。 此外，外壳的壁和/或顶部可以被电镀以提供在壳体上和周围连接容纳部件或任何其它部件的多功能性。 壳体上的电镀可以连接到围绕开口的电镀和在下边缘的平坦部分处的电镀，或者可以完全独立于所容纳的电子部件。

公开(公告)号：US5789271A

公开(公告)日：1998-08-04

申请号：US617283

申请日：1996-03-18

Applicant: Salman Akram

Inventor： Salman Akram

IPC: H01L21/48 ,  H01L23/498 ,  H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/14 ,  H05K3/28 ,  H05K3/32 ,  H05K3/34 ,  H05K3/40 ,  H05K3/46 ,  H01L21/00

CPC classification number: H05K1/113 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49827 ,  H05K3/4007 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/19107 ,  H05K1/0271 ,  H05K1/0306 ,  H05K2201/0133 ,  H05K2201/0154 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2203/043 ,  H05K3/143 ,  H05K3/28 ,  H05K3/325 ,  H05K3/3457 ,  H05K3/4605 ,  H05K3/4676

Abstract: A method for forming an interconnect for making a temporary or permanent electrical connection to a semiconductor dice is provided. The interconnect includes a rigid substrate on which an insulating layer and a pattern of conductors are formed. A compliant layer is formed on the insulating layer of a material such as polyimide. Vias are formed in the compliant layer with metal contacts in electrical communication with the conductors. Microbumps are formed on the compliant layer in electrical communication with the contacts and are adapted to flex with the compliant layer. The interconnect can be used to provide a temporary electrical connection for testing bare semiconductor dice. Alternately the interconnect can be used for flip chip mounting dice for fabricating multi chip modules and other electronic devices.

Abstract translation: 提供了一种用于形成用于制造与半导体裸片的暂时或永久电连接的互连的方法。 互连包括刚性基板，其上形成绝缘层和导体图案。 柔性层形成在诸如聚酰亚胺的材料的绝缘层上。 在兼容层中形成通孔，其中金属触点与导体电连通。 微胶囊形成在柔性层上，与触头电连通并且适于与柔顺层挠曲。 互连可用于提供用于测试裸半导体裸片的临时电连接。 或者，互连可以用于倒装芯片安装芯片，用于制造多芯片模块和其他电子设备。

公开(公告)号：US5636104A

公开(公告)日：1997-06-03

申请号：US512013

申请日：1995-08-07

Applicant: Sang E. Oh

Inventor： Sang E. Oh

IPC: H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H05K3/34 ,  H05K3/46 ,  H05K7/02 ,  H01R9/09

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49827 ,  H05K3/3436 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10242 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613

Abstract: A ball grid array package includes a semiconductor chip 4, a circuit board 21 including a plurality of pattern layers of conductive wiring and dielectric layers interposed between the pattern layers which include the first pattern layer 22 and the second pattern layer 23. Electrically conductive wires are provided for interconnecting the semiconductor chip and the conductive wiring, mold resin 4 encapsulates the semiconductor chip and the wiring, and a plurality of solder balls 5 are adhered to a bottom surface of the circuit board 21 and electrically interconnected to the wires via the pattern layers. The surface mounting pad 22 is formed on the first pattern layer and a second conductive pad is formed on the second pattern layer. The first pattern layer is an outermost layer of the circuit board and the second pattern layer is just inside of the first layer so that the first and the second conductive pads form a solder ball groove mounting pad wherein a bottom surface of the mounting pad is the second conductive pad and the first conductive pad extends to the surface of the mounting pad.

Abstract translation: 球栅阵列封装包括半导体芯片4，电路板21，其包括插入在包括第一图案层22和第二图案层23的图案层之间的导电布线和电介质层的多个图案层。导电导线 提供用于互连半导体芯片和导电布线，模制树脂4封装半导体芯片和布线，并且多个焊球5粘附到电路板21的底表面并且经由图案层电连接到导线 。 表面安装焊盘22形成在第一图案层上，第二导电焊盘形成在第二图案层上。 第一图案层是电路板的最外层，第二图案层刚好在第一层的内部，使得第一和第二导电焊盘形成焊球保持垫，其中安装垫的底表面是 第二导电焊盘和第一导电焊盘延伸到安装焊盘的表面。

公开(公告)号：US5628919A

公开(公告)日：1997-05-13

申请号：US439980

申请日：1995-05-12

Applicant: Yoshihiro Tomura ,  Yoshihiro Bessho ,  Yasuhiko Hakotani

Inventor： Yoshihiro Tomura ,  Yoshihiro Bessho ,  Yasuhiko Hakotani

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/485 ,  H01L23/498 ,  H05K1/18 ,  H05K3/24 ,  H05K3/32 ,  H05K3/40 ,  B44C1/22

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H05K3/321 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H05K1/181 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/09845 ,  H05K2201/10568 ,  H05K2201/10719 ,  H05K2201/10984 ,  H05K2203/0577 ,  H05K2203/167 ,  H05K3/243

Abstract: A chip carrier according to the present invention includes: a carrier body including an upper face, a lower face, and an internal conductor; and a plurality of terminal electrodes formed on the upper face of the carrier body, the plurality of terminal electrodes electrically connecting an LSI chip to the internal conductor. A plurality of concave portions for electrically connecting a plurality of electrodes on a circuit substrate to the internal conductor are provided on the lower face of the carrier body, the concave portions being electrically connected to the internal conductor.

Abstract translation: 根据本发明的芯片载体包括：载体，其包括上表面，下表面和内导体; 以及形成在所述载体主体的上表面上的多个端子电极，所述多个端子电极将LSI芯片电连接到所述内部导体。 多个用于将电路基板上的多个电极电连接到内部导体的凹部设置在载体主体的下表面上，凹部电连接到内部导体。

公开(公告)号：US5608265A

公开(公告)日：1997-03-04

申请号：US207697

申请日：1994-03-09

Applicant: Makoto Kitano ,  Asao Nishimura ,  Akihiro Yaguchi ,  Nae Yoneda ,  Ryuji Kohno ,  Naotaka Tanaka ,  Tetsuo Kumazawa

Inventor： Makoto Kitano ,  Asao Nishimura ,  Akihiro Yaguchi ,  Nae Yoneda ,  Ryuji Kohno ,  Naotaka Tanaka ,  Tetsuo Kumazawa

IPC: H01L21/56 ,  H01L23/12 ,  H01L23/13 ,  H01L23/28 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H01L25/10 ,  H01L25/11 ,  H01L25/16 ,  H01L25/18 ,  H05K1/18 ,  H05K3/34 ,  H01L23/48 ,  H01L23/02 ,  H01L29/40

CPC classification number: H01L23/3107 ,  H01L21/565 ,  H01L23/13 ,  H01L23/4951 ,  H01L23/49541 ,  H01L25/105 ,  H01L25/16 ,  H05K1/181 ,  H05K3/3436 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H05K2201/09472 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10818 ,  H05K2201/10931 ,  H05K3/3426 ,  H05K3/3431 ,  Y02P70/611 ,  Y02P70/613

Abstract: A semiconductor device, provided in a plastic encapsulated package, having a semiconductor chip, a lead and a member for electrically connecting them together. The semiconductor device has one or more first holes respectively extending from one surface of the package to a first side of the lead which is provided inside of the package, and has one or more second holes formed which are aligned with the first holes, respectively, in a manner such that each second hole is extended from the opposing surface of the package to a corresponding location on a second side of the lead and is aligned with a corresponding, opposing first hole, in the package, extending to the first side of the lead. These holes are provided as a plurality of sets of individual pairs of aligned holes respectively extending inwardly, from opposing surfaces of the package, to opposite sides of the corresponding leads. In the device the leads or the leads with resin act as partitions thereby effecting isolation between the first and second holes of each pair aligned holes.

Abstract translation: 设置在塑料封装封装中的半导体器件具有半导体芯片，引线和用于将它们电连接在一起的部件。 半导体器件具有分别从封装的一个表面延伸到设置在封装内部的引线的第一侧的一个或多个第一孔，并且分别具有与第一孔对准的一个或多个第二孔， 以使得每个第二孔从包装的相对表面延伸到引线的第二侧上的对应位置并且与包装中的相应的相对的第一孔对准，延伸到包装的第一侧 铅。 这些孔被设置为多组对齐的对齐的孔，分别从包装的相对表面向内延伸到相应引线的相对侧。 在装置中，引线或具有树脂的引线作为隔板，从而实现每对对齐的孔的第一和第二孔之间的隔离。