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    APPARATUS AND METHODS FOR VIA CONNECTION WITH REDUCED VIA CURRENTS
    171.
    发明申请
    APPARATUS AND METHODS FOR VIA CONNECTION WITH REDUCED VIA CURRENTS 审中-公开

    公开(公告)号：US20180192517A1

    公开(公告)日：2018-07-05

    申请号：US15854598

    申请日：2017-12-26

    Applicant: Micron Technology, Inc.

    Inventor： Atsushi Morishima

    IPC: H05K1/11 ,  H05K1/18

    CPC classification number: H05K1/115 ,  H05K1/025 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/0776 ,  H05K2201/09227 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2201/0979

    Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

    Apparatus and methods for via connection with reduced via currents
    175.
    发明授权
    Apparatus and methods for via connection with reduced via currents 有权

    公开(公告)号：US09888574B1

    公开(公告)日：2018-02-06

    申请号：US15399664

    申请日：2017-01-05

    Applicant: Micron Technology, Inc.

    Inventor： Atsushi Morishima

    IPC: H05K7/00 ,  H05K1/11 ,  H05K1/18

    CPC classification number: H05K1/115 ,  H05K1/025 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/0776 ,  H05K2201/09227 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2201/0979

    Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

    CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS
    176.
    发明申请
    CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS 审中-公开

    公开(公告)号：US20170324208A1

    公开(公告)日：2017-11-09

    申请号：US15659351

    申请日：2017-07-25

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： DARKO R. POPOVIC

    IPC: H01R43/20 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50 ,  H01L23/552

    CPC classification number: H01R43/205 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/552 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0228 ,  H05K1/0245 ,  H05K2201/09609 ,  H05K2201/09636

    Abstract: Embodiments reduce crosstalk between electrical interconnects by offsetting pairs of electrical interconnects in an electrical system to produce a staggered interconnect pattern for which magnetic flux through a loop formed by a victim interconnect pair is effectively canceled. Magnetic field vectors generated by an aggressor pair of interconnects can pass through a loop-bounded surface defined by a victim pair of interconnects in the system. In the staggered interconnect pattern, the victim interconnect pair is offset with respect to the aggressor interconnect pair so that the field vectors passing through the victim pair's loop-bounded surface in one direction are substantially balanced by the field vectors passing through the victim pair's loop-bounded surface in the opposite direction, thereby minimizing the effect of the aggressor pair's magnetic field on the victim pair. Since crosstalk is proportional to the rate of change of the magnetic flux, reducing the magnetic flux can reduce the crosstalk.

    Breakout via system
    177.
    发明授权
    Breakout via system 有权

    公开(公告)号：US09769926B2

    公开(公告)日：2017-09-19

    申请号：US14694759

    申请日：2015-04-23

    Applicant: Dell Products L.P.

    Inventor： Kevin Warren Mundt ,  Sandor Farkas ,  Bhyrav Mutnury

    IPC: H05K1/11 ,  H05K1/02 ,  G06F1/20 ,  G06F1/18

    CPC classification number: H05K1/114 ,  G06F1/185 ,  G06F1/20 ,  H05K1/0222 ,  H05K1/0251 ,  H05K2201/09609 ,  H05K2201/09636

    Abstract: A circuit board includes a board base with a first surface and a second surface that is located opposite the first surface. A plurality of first coupling pads are located on the first surface of the board base. A plurality of second coupling pads are located on the second surface of the board base. The first coupling pads and the second coupling pads define a coupling pad footprint. A breakout via system is included in the board base. The breakout via system includes a plurality of primary signal vias that are located in the board base and outside of the coupling pad footprint, a plurality of first primary signal via connections that extend between the primary signal vias and the plurality of first coupling pads, and a plurality of second primary signal via connections that extend between the primary signal vias and the plurality of second coupling pads.

    Printed circuit board structure with heat dissipation function
    179.
    发明授权
    Printed circuit board structure with heat dissipation function 有权
    印刷电路板结构具有散热功能

    公开(公告)号：US09554453B2

    公开(公告)日：2017-01-24

    申请号：US13777369

    申请日：2013-02-26

    Applicant: MediaTek Inc.

    Inventor： Shu-Wei Hsiao

    IPC: H05K1/00 ,  H05K1/02

    CPC classification number: H05K1/0209 ,  H05K1/0206 ,  H05K2201/09609 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10727 ,  H05K2201/10969

    Abstract: A printed circuit board (PCB) structure with a heat dissipation function is provided, including: a package substrate; a landing pad formed over a portion of the package substrate from a first surface thereof, wherein the landing pad has a rectangular configuration and has a plurality of corners; a plurality of ground traces formed over various portions of the package substrate, physically connecting to the bond pad from at least two of the corners thereof, respectively; a first through hole formed through the landing pad and the package substrate from substantially a center portion of the bonding pad; and a plurality of second through holes formed through the landing pad and the package substrate from substantially one of the corners of the bonding pad, wherein the second through holes are adjacent to the ground traces, respectively.

    Abstract translation: 提供具有散热功能的印刷电路板（PCB）结构，包括：封装基板; 从所述封装基板的第一表面形成在所述封装基板的一部分上的着陆焊盘，其中所述着陆焊盘具有矩形构造并且具有多个拐角; 形成在所述封装衬底的各个部分上的多个接地迹线，分别从其至少两个角部物理连接到所述接合焊盘; 从接合焊盘的大致中心部分穿过着陆焊盘和封装衬底形成的第一通孔; 以及多个第二通孔，其通过所述着陆焊盘和所述封装基板从所述接合焊盘的大致角部形成，其中所述第二通孔分别与所述接地迹线相邻。

    Printed Wiring Board
    180.
    发明申请
    Printed Wiring Board 审中-公开
    印刷线路板

    公开(公告)号：US20160309592A1

    公开(公告)日：2016-10-20

    申请号：US15099905

    申请日：2016-04-15

    Applicant: Rohm Co., Ltd.

    Inventor： Masashi Nagasato

    IPC: H05K1/18 ,  H05K1/02

    CPC classification number: H05K1/0243 ,  H05K1/0242 ,  H05K1/025 ,  H05K3/4685 ,  H05K2201/09154 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/10053 ,  H05K2201/1009 ,  H05K2201/10704 ,  H05K2201/10719 ,  H05K2201/10734

    Abstract: A printed wiring board used to suppress parasitic component is provided. The printed wiring board 100 includes a multi-layer substrate 110, and a power line 50 laid on the multi-layer substrate 110 and connected with a power terminal row T11a-T11d of a semiconductor device 10. The power line 50 includes a first wiring pattern 51 formed on a surface of the multi-layer substrate 110, a second wiring pattern 52 formed within the multi-layer substrate 110, and interlayer connections 53x and 53y electrically conducting the first wiring pattern 51 and the second wiring pattern 52 to bypass at least a portion of the power terminal row T11a-T11d.

    Abstract translation: 提供了用于抑制寄生成分的印刷线路板。 印刷电路板100包括多层基板110和布置在多层基板110上并与半导体装置10的电源端子排T11a-T11d连接的电力线50.电力线50包括第一布线 形成在多层基板110的表面上的图案51，形成在多层基板110内的第二布线图案52，以及导电第一布线图案51和第二布线图案52旁路的层间连接53x和53y 电力端子排T11a-T11d的至少一部分。

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