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    WIRING DEVICE AND DISPLAY DEVICE
    172.
    发明申请
    WIRING DEVICE AND DISPLAY DEVICE 有权
    接线装置和显示装置

    公开(公告)号：US20120314379A1

    公开(公告)日：2012-12-13

    申请号：US13227485

    申请日：2011-09-08

    Applicant: Tsu-Te Zen

    Inventor： Tsu-Te Zen

    IPC: H05K1/11 ,  H05K7/00

    CPC classification number: G02F1/13452 ,  H05K1/114 ,  H05K2201/09254 ,  H05K2201/0979

    Abstract: A wiring device includes a main conductive line, a plurality of branch conductive lines, a passivation layer, a plurality of contact holes, a plurality of conductive patterns, and a plurality of outside device bonding regions. The branch conductive lines are electrically connected to the main conductive line. The passivation layer is disposed on the branch conductive lines. Each the contact hole partially exposes one of the branch conductive lines. The conductive patterns are disposed on the passivation layer, and each of the conductive patterns is disposed respectively corresponding to each of the branch conductive lines. Each of the conductive patterns is electrically connected to the corresponding branch conductive line via the contact holes. Each of the outside device bonding regions is disposed corresponding to each of the branch conductive lines. At least one of the outside device bonding regions does not overlap the contact hole in a vertical projective direction.

    Abstract translation: 布线装置包括主导线，多个分支导线，钝化层，多个接触孔，多个导电图案以及多个外部装置接合区域。 分支导线与主导线电连接。 钝化层设置在分支导电线上。 每个接触孔部分地暴露一条分支导电线。 导电图案设置在钝化层上，并且每个导电图案分别对应于每个分支导电线设置。 每个导电图案经由接触孔电连接到相应的分支导电线。 每个外部装置接合区域对应于每个分支导电线设置。 外部装置接合区域中的至少一个在垂直投射方向上不与接触孔重叠。

    LED PACKAGE STRUCTURE
    173.
    发明申请
    LED PACKAGE STRUCTURE 有权
    LED封装结构

    公开(公告)号：US20120273806A1

    公开(公告)日：2012-11-01

    申请号：US13096761

    申请日：2011-04-28

    Applicant: CHAO-CNIN WU ,  Shen-Ta Yang

    Inventor： CHAO-CNIN WU ,  Shen-Ta Yang

    IPC: H01L27/15

    CPC classification number: H01L25/0753 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/73265 ,  H05K1/11 ,  H05K2201/0979 ,  H05K2201/10106 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: An LED package structure with standby bonding pads for increasing wire-bonding yield includes a substrate unit, a light-emitting unit, a conductive wire unit and a package unit. The substrate unit has a substrate body and a plurality of positive pads and negative pads. The light-emitting unit has a plurality of LED bare chips. The positive electrode of each LED bare chip corresponds to at least two of the positive pads, and the negative electrode of each LED bare chip corresponds to at least two of the negative pads. Each wire is electrically connected between the positive electrode of the LED bare chip and one of the at least two positive pads or between the negative electrode of the LED bare chip and one of the at least two negative pads. The package unit has a light-permitting package resin body on the substrate body to cover the LED bare chips.

    Abstract translation: 具有用于提高引线接合成品率的备用接合焊盘的LED封装结构包括基板单元，发光单元，导线单元和封装单元。 基板单元具有基板主体和多个正极焊盘和负极焊盘。 发光单元具有多个LED裸芯片。 每个LED裸芯片的正极对应于至少两个正极焊盘，并且每个LED裸芯片的负电极对应于至少两个负极焊盘。 每条导线电连接在LED裸芯片的正电极和至少两个正极焊盘中的一个之间或LED裸芯片的负电极之间以及至少两个负焊盘中的一个之间。 封装单元在基板主体上具有允许封装的树脂体，以覆盖LED裸芯片。

    INTERPOSER HAVING MOLDED LOW CTE DIELECTRIC
    174.
    发明申请
    INTERPOSER HAVING MOLDED LOW CTE DIELECTRIC 有权
    具有成型低CTE电介质的插件

    公开(公告)号：US20120267751A1

    公开(公告)日：2012-10-25

    申请号：US13091800

    申请日：2011-04-21

    Applicant: Belgacem Haba ,  Ilyas Mohammed

    Inventor： Belgacem Haba ,  Ilyas Mohammed

    IPC: H01L23/482 ,  H01L27/02 ,  H01L21/28

    CPC classification number: H01L21/486 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K3/4046 ,  H05K2201/0979 ,  H05K2201/10378 ,  H05K2201/10674

    Abstract: A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.

    Abstract translation: 公开了一种用于制造互连部件的方法，包括形成远离参考表面延伸的多个金属柱。 每个柱形成具有一对相对的端面和在它们之间延伸的边缘表面。 形成接触边缘表面和相邻柱之间的填充空间的电介质层。 电介质层具有邻近第一和第二端面的第一和第二相对表面。 电介质层的热膨胀系数小于8ppm /℃。互连部件完成，使得它们在横向方向上延伸的柱的第一和第二端面之间没有互连。 第一和第二多个可湿接触部分邻近第一和第二相对表面。 可湿接触可用于将互连部件连接到微电子元件或电路板。

    CERAMIC SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
    175.
    发明申请
    CERAMIC SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME 有权
    陶瓷基板及其制造方法

    公开(公告)号：US20120247821A1

    公开(公告)日：2012-10-04

    申请号：US13436005

    申请日：2012-03-30

    Applicant: Toshihisa NOMURA ,  Kenji SUZUKI ,  Kazushige AKITA

    Inventor： Toshihisa NOMURA ,  Kenji SUZUKI ,  Kazushige AKITA

    IPC: H05K1/00 ,  B32B38/10 ,  B05D5/12

    CPC classification number: H05K1/0287 ,  G01R1/07342 ,  G01R3/00 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/005 ,  H05K3/4061 ,  H05K3/429 ,  H05K2201/0949 ,  H05K2201/09609 ,  H05K2201/0979 ,  Y10T156/11

    Abstract: A ceramic substrate for an electronic part inspecting apparatus that can be manufactured in accordance with predetermined specifications, regardless of the number and location of pins required, relatively quickly and inexpensively is provided. In certain embodiments the ceramic substrate is configured to connect to a probe for inspecting an electronic component, and the ceramic substrate comprises a plurality of vias located in a center area of the ceramic substrate that penetrate through the ceramic substrate in its thicknesswise direction, pads located in an outer periphery that surrounds the center area where the vias are located, the pads being configured to connected to the probes, and a conductive layer located only over the front surface of the ceramic substrate and connects the vias to the respective pads. Certain embodiments comprise a greater number of vias than pins. A method of manufacturing the ceramic substrate is also provided.

    Abstract translation: 提供了一种用于电子部件检查装置的陶瓷基板，其可以根据预定规格制造，而不管所需的销的数量和位置如何，相对快速且低成本地进行。 在某些实施例中，陶瓷衬底被配置为连接到用于检查电子部件的探针，并且陶瓷衬底包括位于陶瓷衬底的沿其厚度方向穿过陶瓷衬底的中心区域的多个通孔，位于 在围绕通孔所在的中心区域的外周中，衬垫被配置为连接到探针，以及导电层，其仅位于陶瓷衬底的前表面上，并将通孔连接到相应的焊盘。 某些实施例包括比引脚更多的通孔。 还提供了制造陶瓷基板的方法。

    Printed wiring board and electronic-component package
    176.
    发明授权
    Printed wiring board and electronic-component package 有权
    印刷电路板和电子元件封装

    公开(公告)号：US08222540B2

    公开(公告)日：2012-07-17

    申请号：US12775916

    申请日：2010-05-07

    Applicant: Akiyoshi Saitou

    Inventor： Akiyoshi Saitou

    IPC: H05K1/11

    CPC classification number: H05K1/0251 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0242 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/09627 ,  H05K2201/0979 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    Abstract: A printed wiring board having an insulating core; a plurality of vias having axes parallel to and at equal distance from a reference axis and passing through the core; a first conductive film formed on a front surface of the core from the reference axis to each of the individual vias; a first insulating film stacked on the front surface of the core and covering the first conductive film; a first connecting via having an axis identical to the reference axis and passing through the first stacked film; a second conductive film formed on a back surface of the core from the reference axis to each of the individual vias; a second insulating film stacked on the back surface of the core and covering the second conductive film; and a second connecting via having an axis identical to the reference axis and passing through the second stacked film.

    Abstract translation: 一种具有绝缘芯的印刷线路板; 多个通孔具有平行于参考轴线并且距离参考轴线等距离并且穿过芯部的轴线; 第一导电膜，其形成在所述芯的前表面上，从参考轴线到每个所述各个通孔; 第一绝缘膜，堆叠在所述芯的前表面上并覆盖所述第一导电膜; 第一连接通孔，其具有与参考轴线相同的轴线并穿过第一层叠膜; 形成在所述芯的背面上的第二导电膜，所述第二导电膜从所述参考轴线到每个所述各个通孔; 层叠在所述芯的背面上并覆盖所述第二导电膜的第二绝缘膜; 以及第二连接通孔，其具有与参考轴线相同的轴线并且穿过第二层叠膜。

    Laminated body and manufacturing method thereof
    177.
    发明授权
    Laminated body and manufacturing method thereof 有权
    层压体及其制造方法

    公开(公告)号：US08193898B2

    公开(公告)日：2012-06-05

    申请号：US12529700

    申请日：2008-02-28

    Applicant: Isao Tonouchi

    Inventor： Isao Tonouchi

    IPC: H01C7/18

    CPC classification number: H01C1/14 ,  H01C7/003 ,  H01C7/18 ,  H01C17/28 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/167 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09672 ,  H05K2201/0979

    Abstract: A laminated body and fabrication method thereof, which allow space saving and control of variation in internal layer resistance, are provided. When forming an internal-layer resistive element 7 in a multilayer ceramic substrate 10, the internal-layer resistive element 7 is connected to exterior electrodes (an upper surface electrode 32 and an undersurface electrode 34) via multiple via-electrodes 3a and 3b arranged in parallel, without a pad electrode adopted in the conventional laminated body. Moreover, in a multilayer ceramic substrate having multiple internal-layer resistive elements arranged in a multilayer structure, multiple internal-layer resistive elements are directly connected via multiple via-electrodes arranged in parallel.

    Abstract translation: 提供了能够节省空间并控制内层电阻的变化的层叠体及其制造方法。 当在多层陶瓷衬底10中形成内层电阻元件7时，内层电阻元件7通过多个通孔电极3a和3b连接到外电极（上表面电极32和下表面电极34） 平行的，在常规层压体中没有采用焊盘电极。 此外，在具有以多层结构排列的多个内层电阻元件的多层陶瓷基板中，多个内层电阻元件通过并联布置的多个通孔电极直接连接。

    PRINTED CIRCUIT BOARD
    178.
    发明申请
    PRINTED CIRCUIT BOARD 审中-公开
    印刷电路板

    公开(公告)号：US20120132461A1

    公开(公告)日：2012-05-31

    申请号：US12981477

    申请日：2010-12-30

    Applicant: TSUNG-SHENG HUANG

    Inventor： TSUNG-SHENG HUANG

    IPC: H05K1/16

    CPC classification number: H05K1/0265 ,  H05K1/0201 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0979

    Abstract: A printed circuit board includes a top layer and a bottom layer. A power supply and an electronic component are located on the top layer. The power supply is connected to the top layer and the bottom layer through a first via. A number of second vias extend through the printed circuit board and are connected to the top layer and the bottom layer. The distance between each second via and the electronic component is the same.

    Abstract translation: 印刷电路板包括顶层和底层。 电源和电子元件位于顶层。 电源通过第一通孔连接到顶层和底层。 多个第二通孔延伸穿过印刷电路板并连接到顶层和底层。 每个第二通孔和电子部件之间的距离是相同的。

    SPLIT WAVE COMPENSATION FOR OPEN STUBS
    179.
    发明申请
    SPLIT WAVE COMPENSATION FOR OPEN STUBS 审中-公开
    开放波段的分波补偿

    公开(公告)号：US20120055016A1

    公开(公告)日：2012-03-08

    申请号：US13292674

    申请日：2011-11-09

    Applicant: Dan Gorcea

    Inventor： Dan Gorcea

    IPC: H01K3/10

    CPC classification number: H05K1/0248 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09336 ,  H05K2201/09627 ,  H05K2201/0979 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/31511

    Abstract: In accordance with a first embodiment, the present invention provides a circuit substrate comprising a first surface; a second surface; a first via having a first end near said first surface and a second end near said second surface; a second via having a first end near said first surface and a second end near said second surface; a first conductive element electrically coupling said first end of said first via and said first end of said second via; a second conductive element electrically coupling said second end of said first via and said second end of said second via; an input signal line coupled to said first via; and an output signal line coupled to said second via.

    Abstract translation: 根据第一实施例，本发明提供了一种包括第一表面的电路基板; 第二表面 具有靠近所述第一表面的第一端和靠近所述第二表面的第二端的第一通孔; 第二通孔，其具有靠近所述第一表面的第一端和靠近所述第二表面的第二端; 电连接所述第一通孔的所述第一端和所述第二通孔的所述第一端的第一导电元件; 电连接所述第一通孔的所述第二端和所述第二通孔的所述第二端的第二导电元件; 耦合到所述第一通孔的输入信号线; 以及耦合到所述第二通孔的输出信号线。

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