公开(公告)号：US20180295723A1

公开(公告)日：2018-10-11

申请号：US16008060

申请日：2018-06-14

Applicant: Unimicron Technology Corp.

Inventor： Ming-Hao Wu ,  Wen-Fang Liu

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K1/111 ,  H05K1/115 ,  H05K3/0044 ,  H05K3/3452 ,  H05K3/4697 ,  H05K2201/0376 ,  H05K2203/0228 ,  H05K2203/025

Abstract: A manufacturing method of a circuit board structure includes the following steps: providing an inner circuit structure which includes a core layer; performing a build-up process to laminate a first build-up circuit structure on a first patterned circuit layer of the inner circuit structure, wherein the first build-up circuit structure includes an inner dielectric layer, and the inner dielectric layer directly covers an upper surface of the core layer and the first patterned circuit layer; removing a portion of the first build-up circuit structure to form an opening extending from a first surface of the first build-up circuit structure relatively far away from the inner circuit structure to a portion of the inner dielectric layer; performing a sandblasting process on a first inner surface of the inner dielectric layer exposed by the opening to at least remove the portion of the inner dielectric layer exposed by the opening.

公开(公告)号：US10083901B2

公开(公告)日：2018-09-25

申请号：US15853926

申请日：2017-12-25

Applicant: Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Cheng-Ta Ko

IPC: H05K3/46 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/096 ,  H05K2201/10378

Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.

公开(公告)号：US10039184B2

公开(公告)日：2018-07-31

申请号：US15427061

申请日：2017-02-08

Applicant: Unimicron Technology Corp.

Inventor： Ming-Hao Wu ,  Wen-Fang Liu

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K1/111 ,  H05K1/115 ,  H05K3/0044 ,  H05K3/3452 ,  H05K3/4697 ,  H05K2201/0376 ,  H05K2203/0228 ,  H05K2203/025

Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface opposite to each other, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive via connecting the first and the second patterned circuit layers. The first build-up circuit structure is disposed on the upper surface of the core layer and covers the first patterned circuit layer, wherein the first build-up circuit structure at least has a cavity, the cavity exposes a portion of the first patterned circuit layer and a cross-sectional profile of an edge of a top surface of the portion of the first patterned circuit layer exposed by the cavity is a curved surface.

公开(公告)号：US20180077799A1

公开(公告)日：2018-03-15

申请号：US15822222

申请日：2017-11-27

Applicant: Unimicron Technology Corp.

Inventor： Ming-Hao Wu ,  Shu-Sheng Chiang ,  Wei-Ming Cheng

IPC: H05K1/11 ,  H05K1/09 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/111 ,  H05K1/0266 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/0073 ,  H05K3/4038 ,  H05K3/4092 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/09036 ,  H05K2201/094 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/0376 ,  H05K2203/163

Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening communicating the cavity and a pad of the first patterned circuit layer is located in the opening. A hole diameter of the opening is smaller than a hole diameter of cavity. An inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference.

公开(公告)号：US20180014409A1

公开(公告)日：2018-01-11

申请号：US15201622

申请日：2016-07-05

Applicant: Unimicron Technology Corp.

Inventor： Chien-Tsai Li ,  Chien-Te Wu ,  Cheng-Chung Lo

IPC: H05K3/40 ,  H01L21/683 ,  H05K3/22 ,  H05K3/46

CPC classification number: H05K3/4038 ,  H05K3/22 ,  H05K3/4644

Abstract: Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A dicing process is performed, such that at least one slit is formed in the glass film. A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on the glass film. A polymer layer is formed on the first circuit layer. The polymer layer covers surfaces of the first circuit layer and the glass film. A plurality of second conductive vias are formed in the polymer layer. A second circuit layer is formed on the polymer layer, such that a first circuit board structure is formed. A singulation process is performed, such that the first circuit board structure is divided into a plurality of second circuit board structures.

公开(公告)号：US20170273186A1

公开(公告)日：2017-09-21

申请号：US15255150

申请日：2016-09-02

Applicant: Unimicron Technology Corp.

Inventor： Shih-Lian Cheng

IPC: H05K3/00 ,  H05K3/10 ,  H05K3/46

CPC classification number: H05K3/064 ,  G03F7/0002 ,  G03F7/162 ,  G03F7/20 ,  H05K1/115 ,  H05K3/0023 ,  H05K3/06 ,  H05K3/108 ,  H05K3/4644 ,  H05K3/465 ,  H05K2201/091 ,  H05K2203/0108 ,  H05K2203/0369 ,  H05K2203/0502 ,  H05K2203/0548 ,  H05K2203/0562 ,  Y10T29/49124 ,  Y10T29/49155

Abstract: A manufacturing method of a circuit board including the following steps is provided. A carrier substrate is provided. A patterned photoresist layer is formed on the carrier substrate. An adhesive layer is formed on the top surface of the patterned photoresist layer. A dielectric substrate is provided. A circuit pattern and a dielectric layer covering the circuit pattern are formed on the dielectric substrate, wherein the dielectric layer has an opening exposing a portion of the circuit pattern. The adhesive layer is adhered to the dielectric layer in a direction that the adhesive layer faces of the dielectric layer. The carrier substrate is removed. A patterned metal layer is formed on a region exposed by the patterned photoresist layer. The patterned photoresist layer is removed. The adhesive layer is removed.

公开(公告)号：US20170196095A1

公开(公告)日：2017-07-06

申请号：US15058138

申请日：2016-03-01

Applicant: Unimicron Technology Corp.

Inventor： Hung-Lin Chang ,  Chen-Wei Tseng

IPC: H05K3/46 ,  H05K1/09 ,  H05K1/02

CPC classification number: H05K3/4679 ,  H05K1/0266 ,  H05K2201/083 ,  H05K2201/09936

Abstract: A circuit board includes a core layer, at least one metal contraposition component and at least one build-up circuit structure. The metal contraposition component is disposed on the core layer. The build-up circuit structure is disposed on the core layer and covers the metal contraposition component by using a position of the metal contraposition component as a fiducial mark.

公开(公告)号：US20170194249A1

公开(公告)日：2017-07-06

申请号：US15468087

申请日：2017-03-23

Applicant: Industrial Technology Research Institute ,  Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Wei-Chung Lo ,  Dyi-Chung Hu ,  Chang-Hong Hsieh

IPC: H01L23/522 ,  H01L21/48 ,  H01L25/04 ,  H01L23/498

CPC classification number: H01L23/5226 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/04 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.

公开(公告)号：US20170125337A1

公开(公告)日：2017-05-04

申请号：US14931808

申请日：2015-11-03

Applicant: Unimicron Technology Corp.

Inventor： Chia-Chan Chang ,  Gwo-Chaur Chen ,  Yung-Tsai Chen

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H05K1/09 ,  H01L21/4846 ,  H01L21/4875 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2924/1531 ,  H01L2924/3511 ,  H05K1/181 ,  H05K3/007 ,  H05K3/188 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y02P70/613

Abstract: A method for manufacturing a circuit structure is described as follows. Two patterned circuit layers are formed on a core layer. The patterned circuit layers are located on two opposite surfaces of the core layer. A patterned insulating layer is respectively formed on each of the patterned circuit layers. The patterned insulating layers respectively expose a portion of the patterned circuit layers. The core layer is removed so as to expose an upper surface of each of the patterned circuit layers and a top surface of each of the patterned insulating layers. The upper surface of each of the patterned circuit layers is aligned with the top surface of each of the patterned insulating layers.

公开(公告)号：US20170055349A1

公开(公告)日：2017-02-23

申请号：US14833129

申请日：2015-08-23

Applicant: Unimicron Technology Corp.

Inventor： Hung-Lin Chang ,  Ta-Han Lin

IPC: H05K1/18 ,  H05K1/03 ,  H05K3/46 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/186 ,  H01L23/3121 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2924/15153 ,  H01L2924/19105 ,  H05K1/0298 ,  H05K1/0326 ,  H05K1/0333 ,  H05K1/0346 ,  H05K1/111 ,  H05K1/115 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/0129 ,  H05K2201/0145 ,  H05K2201/09081 ,  H05K2201/09545

Abstract: A package structure includes a circuit substrate, at least one electronic component, and a connecting slot. The circuit substrate includes at least one core layer, a build-up structure including at least three patterned circuit layers, at least two dielectric layers and conductive through holes, and circuit pads. The electronic component is embedded in at least one of the dielectric layers and located in a disposition area. The electronic component is electrically connected to one of the patterned circuit layers through a portion of the conductive through holes. The connecting slot has a bottom portion, a plurality of sidewall portions connecting the bottom portion, and a plurality of connecting pads located on the sidewall portions. The circuit substrate is assembled to the bottom portion, and the circuit pads are electrically connected to the connecting pads through a bent area of the core layer that is bent relative to the disposition area.

Abstract translation: 封装结构包括电路基板，至少一个电子部件和连接槽。 电路基板包括至少一个芯层，包括至少三个图案化电路层，至少两个介电层和导电通孔以及电路板的堆积结构。 电子部件嵌入在至少一个电介质层中并且位于配置区域中。 电子部件通过导电通孔的一部分电连接到图案化电路层之一。 连接槽具有底部，连接底部的多个侧壁部分和位于侧壁部分上的多个连接垫。 电路基板组装到底部，并且电路板通过相对于配置区域弯曲的芯层的弯曲区域电连接到连接焊盘。