公开(公告)号：US20090242247A1

公开(公告)日：2009-10-01

申请号：US12079785

申请日：2008-03-28

Applicant: Aleksandar Aleksov ,  Vladimir Noveski ,  Sujit Sharan ,  Shankar Ganapathysubramanian

Inventor： Aleksandar Aleksov ,  Vladimir Noveski ,  Sujit Sharan ,  Shankar Ganapathysubramanian

IPC: H05K1/09 ,  H05K3/42

CPC classification number: H05K1/0201 ,  H01L21/4807 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/107 ,  H05K3/205 ,  H05K3/388 ,  H05K3/4617 ,  H05K3/4629 ,  H05K3/4647 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

Abstract translation: 描述了用于封装衬底和管芯间隔件的层或层。 层或层包括位于平面内并由金属通孔分开的多个陶瓷阱。 陶瓷井内的凹陷由介电填料材料占据。

公开(公告)号：US20090223043A1

公开(公告)日：2009-09-10

申请号：US12165970

申请日：2008-07-01

Applicant: Ming Cheng Hsu ,  Clinton Chih-Chieh Chao

Inventor： Ming Cheng Hsu ,  Clinton Chih-Chieh Chao

IPC: H05K3/36

CPC classification number: H05K3/243 ,  G01R1/07378 ,  G01R3/00 ,  G01R31/2863 ,  H05K3/108 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/049 ,  H05K2203/0542 ,  H05K2203/0574 ,  Y10T29/49004 ,  Y10T29/4902 ,  Y10T29/49036 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49162 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T29/49204

Abstract: A space transformer for a semiconductor test probe card and method of fabrication. The method may include depositing a first metal layer as a ground plane on a space transformer substrate having a plurality of first contact test pads defining a first pitch spacing, depositing a first dielectric layer on the ground plane, forming a plurality of second test contacts defining a second pitch spacing different than, the first pitch spacing, and forming a plurality of redistribution leads on the first dielectric layer to electrically couple the first contact test pads to the second contact test pads. In some embodiments, the redistribution leads may be built directly on the space transformer substrate. The method may be used in one embodiment to remanufacture an existing space transformer to produce fine pitch test pads having a pitch spacing smaller than the original test pads. In some embodiments, the test pads may be C4 test pads.

Abstract translation: 一种用于半导体测试探针卡的空间变压器及其制造方法。 该方法可以包括在具有限定第一间距间隔的多个第一接触测试焊盘的空间变压器基板上沉积第一金属层作为接地平面，在接地平面上沉积第一介电层，形成多个第二测试触点， 与所述第一间距间隔不同的第二间距间隔，以及在所述第一介电层上形成多个再分配引线，以将所述第一接触测试焊盘电耦合到所述第二接触测试焊盘。 在一些实施例中，再分配引线可以直接构建在空间变换器基板上。 该方法可以在一个实施例中用于重新制造现有空间变压器以产生具有小于原始测试焊盘的间距间距的细间距测试焊盘。 在一些实施例中，测试焊盘可以是C4测试焊盘。

公开(公告)号：US07566834B2

公开(公告)日：2009-07-28

申请号：US12140041

申请日：2008-06-16

Applicant: Tadanori Shimoto ,  Katsumi Kikuchi ,  Hideya Murai ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata

Inventor： Tadanori Shimoto ,  Katsumi Kikuchi ,  Hideya Murai ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata

IPC: H05K1/00

CPC classification number: H01L23/49816 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/145 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0366 ,  H05K3/205 ,  H05K3/423 ,  H05K2201/0376 ,  H05K2201/068 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 μm and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less. (2) D23≧5 (3) D150≧2.5 (4) (D−65/D150)≦3.0 (5) H23≧140 (6) (H−65/H150)≦2.3.

Abstract translation: 布线板具有基底绝缘膜。 基底绝缘膜的厚度为20〜100μm，由玻璃化转变温度为150℃以上的含有玻璃或芳族聚酰胺的增强纤维的耐热性树脂构成。 当T℃温度下的弹性模量为DT（GPa）时，基体绝缘膜具有以下物理性质（1）〜（6）），在温度T℃下的断裂强度为 HT（MPa）。 （1）其厚度方向的热膨胀系数为90ppm / K以下。 （2）D23> = 5（3）D150> = 2.5（4）（D-65 / D150）<= 3.0（5）H23> = 140（6）（H-65 / H150）<= 2.3。

公开(公告)号：US20090178828A1

公开(公告)日：2009-07-16

申请号：US12300184

申请日：2007-06-13

Applicant: Tetsuya Tsumura ,  Hiroharu Nishiyama ,  Etsuo Tsujimoto

Inventor： Tetsuya Tsumura ,  Hiroharu Nishiyama ,  Etsuo Tsujimoto

IPC: H05K7/20 ,  H05K3/00 ,  B05D3/00

CPC classification number: H05K3/202 ,  H01L23/3737 ,  H01L23/49861 ,  H01L24/81 ,  H01L2924/12042 ,  H01L2924/15747 ,  H05K1/0373 ,  H05K1/056 ,  H05K3/027 ,  H05K3/06 ,  H05K2201/0209 ,  H05K2201/0376 ,  H05K2201/09118 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2201/10106 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A heat dissipating wiring board comprises: a metal wiring plate with a circuit pattern formed therein: a filler-containing resin layer embedded with the metal wiring plate such that a top surface of the metal wiring plate is exposed; and a heat dissipating plate arranged on an under surface of the filler-containing resin layer, wherein the circuit pattern is formed of a through groove provided in the metal wiring plate, and this through groove comprises: a fine groove that opens at the top surface of the metal wiring plate; and an expanded groove that expands from a lower end of the fine groove toward the under surface of the metal wiring plate. The heat dissipating wiring board is capable of improving reliability against electric insulation due to a dust or the like in a space of the through groove.

Abstract translation: 散热布线板包括：金属布线板，其中形成有电路图案;一个含有填料的树脂层，嵌入金属布线板，使得金属布线板的顶表面露出; 以及布置在所述含填料的树脂层的下表面上的散热板，其中所述电路图案由设置在所述金属布线板中的通孔形成，并且所述通孔包括：在顶表面开口的细槽 的金属布线板; 以及从所述细槽的下端朝向所述金属配线板的下表面扩展的扩径槽。 散热布线板能够提高通过沟槽的空间中的灰尘等的电绝缘性的可靠性。

公开(公告)号：US20090144972A1

公开(公告)日：2009-06-11

申请号：US12047936

申请日：2008-03-13

Applicant: David C. H. Cheng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

Inventor： David C. H. Cheng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

IPC: H05K3/02

CPC classification number: H05K3/4007 ,  H05K3/06 ,  H05K3/062 ,  H05K3/107 ,  H05K3/3452 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/099 ,  H05K2203/0384 ,  H05K2203/0542 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad.

Abstract translation: 提供一种制造电路板的工艺。 在该过程中，首先，提供包括绝缘层和至少与绝缘层接触的焊盘的电路基板。 接下来，在电路基板上形成阻挡材料层。 阻挡材料层完全覆盖绝缘层和垫。 然后，在阻挡材料层上形成至少一个导电凸块。 导电凸块与焊盘相对，并且阻挡材料层的材料与导电凸块的材料不同。 接下来，通过使用导电凸块作为掩模来去除阻挡材料层的一部分，以暴露绝缘层的表面并形成连接在导电凸块和焊盘之间的阻挡层。

公开(公告)号：US20090065246A1

公开(公告)日：2009-03-12

申请号：US11898103

申请日：2007-09-10

Applicant: Chao-Wen Shih

Inventor： Chao-Wen Shih

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K3/465 ,  H05K3/0023 ,  H05K3/0035 ,  H05K3/045 ,  H05K2201/0376 ,  Y10T29/49155

Abstract: A circuit board disclosed in the present invention includes a core board on which a first circuit layer is placed, wherein the first circuit layer has a plurality of conductive pads; and at least one built-up structure covering the surface of the circuit board, which comprises a dielectric layer, a second circuit layer, and a plurality of conductive vias without being surrounded by annular metal rings. The conductive vias are conducted with the conductive pads of the first circuit layer and the second circuit layer. Besides, the surface of the second circuit layer is in the same height as the surface of the dielectric layer. Also, the present invention provides a method for manufacturing the above-mentioned circuit board structure. Therefore, a circuit board having fine circuits can be formed, and the shape of the circuit can be ensured efficiently. Moreover, electric performances of the circuit board can be improved.

Abstract translation: 本发明公开的电路板包括其上放置有第一电路层的芯板，其中第一电路层具有多个导电焊盘; 以及覆盖电路板的表面的至少一个堆积结构，其包括介电层，第二电路层和多个导电通孔，而不被环形金属环包围。 导电通孔与第一电路层和第二电路层的导电焊盘一起导电。 此外，第二电路层的表面与介电层的表面的高度相同。 此外，本发明提供一种制造上述电路板结构的方法。 因此，可以形成具有精细电路的电路板，并且可以有效地确保电路的形状。 此外，可以提高电路板的电气性能。

公开(公告)号：US20080289863A1

公开(公告)日：2008-11-27

申请号：US11950816

申请日：2007-12-05

Applicant: Chih-kuang Yang ,  Chieh-lin Hsing

Inventor： Chih-kuang Yang ,  Chieh-lin Hsing

IPC: H05K1/09 ,  H05K3/00

CPC classification number: H05K3/4007 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/205 ,  H05K3/243 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/099 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A surface finish structure of multi-layer substrate and manufacturing method thereof. The surface finish structure of the present invention includes a bond pad layer, at least one cover metal layer and a solder mask. The cover metal layer covers the bond pad layer. The solder mask has a hole to expose the cover metal layer. The present invention can form the cover metal layer to cover the bond pad layer and then forms the solder mask. Thereafter, the hole is made to the solder mask at the position of the cover metal layer to expose thereof. Because the bond pad layer is embedded in a dielectric layer of the multi-layer substrate, adhesion intensity between the bond pad layer and the dielectric layer can be enhanced. Meanwhile, contact of the bond pad layer with the solder can be prevented with the cover metal layer.

Abstract translation: 多层基板的表面处理结构及其制造方法。 本发明的表面光洁度结构包括接合焊盘层，至少一个覆盖金属层和焊接掩模。 覆盖金属层覆盖接合焊盘层。 焊接掩模具有用于露出覆盖金属层的孔。 本发明可以形成覆盖金属层以覆盖接合焊盘层，然后形成焊料掩模。 此后，在覆盖金属层的位置处将该孔制成焊料掩模以使其露出。 由于接合焊盘层嵌入在多层基板的电介质层中，所以可以提高接合焊盘层与电介质层之间的粘合强度。 同时，可以通过覆盖金属层来防止接合焊盘层与焊料的接触。

公开(公告)号：US20080258300A1

公开(公告)日：2008-10-23

申请号：US12099322

申请日：2008-04-08

Applicant: Kazuhiro Kobayashi ,  Junichi Nakamura ,  Kentaro Kaneko

Inventor： Kazuhiro Kobayashi ,  Junichi Nakamura ,  Kentaro Kaneko

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/48227 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2201/2072 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which insulating layers of a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128 are provided. The first layer 122 has a first insulating layer 121 and a second insulating layer 123. A protruded portion 132 which is protruded in a radial direction (a circumferential direction) from an outer periphery at one surface side of a first electrode pad 130 is formed on a whole periphery over a boundary surface between the first insulating layer 121 and the second insulating layer 123.

Abstract translation: 半导体器件100具有半导体芯片110被倒装安装在布线板120上的结构。 布线基板120具有多层布线层和多​​层绝缘层的多层结构，并且具有第一层122，第二层124，第三层126和第四层的绝缘层的结构 提供了层128。 第一层122具有第一绝缘层121和第二绝缘层123。 在第一绝缘层121和第二绝缘层121之间的边界面上的整个周边上形成有从第一电极焊盘130的一个表面侧的外周沿径向（周向）突出的突出部132。 层123。

公开(公告)号：US20080257596A1

公开(公告)日：2008-10-23

申请号：US12102303

申请日：2008-04-14

Applicant: Kentaro Kaneko

Inventor： Kentaro Kaneko

IPC: H05K1/11 ,  H05K3/46 ,  H01L21/60

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/48227 ,  H01L2224/81801 ,  H01L2224/85444 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/108 ,  H05K3/205 ,  H05K3/382 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/098 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and a first electrode pad 130 is formed on a chip mounting side. A taper surface 132 of the first electrode pad 130 has a gradient in an orientation reduced in an upward direction toward a solder connecting side or a chip mounting side. Therefore, a holding force for a force applied to the solder connecting side or the chip mounting side is increased, and furthermore, the taper surface 132 adheres to a tapered internal wall of an insulating layer of a first layer so that a bonding strength to the insulating layer is increased.

Abstract translation: 半导体器件100具有半导体芯片110倒装芯片安装在布线板120上的结构。布线板120具有布置多个布线层和多​​个绝缘层的多层结构，并且 第一电极焊盘130形成在芯片安装侧。 第一电极焊盘130的锥形表面132具有沿向上朝向焊接连接侧或芯片安装侧减小的取向的梯度。 因此，施加到焊料连接侧或芯片安装侧的力的保持力增大，此外，锥形表面132粘附到第一层的绝缘层的锥形内壁，使得与 绝缘层增加。

公开(公告)号：US20080210458A1

公开(公告)日：2008-09-04

申请号：US11976848

申请日：2007-10-29

Applicant: Yoshihisa Yamashita ,  Toshio Fujii ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Satoru Tomekawa ,  Hiroki Yabe

Inventor： Yoshihisa Yamashita ,  Toshio Fujii ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Satoru Tomekawa ,  Hiroki Yabe

IPC: H05K1/03

CPC classification number: H05K3/386 ,  H01L51/424 ,  H01L2924/0002 ,  H05K1/16 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4614 ,  H05K2201/0191 ,  H05K2201/0376 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A flexible substrate comprises: (i) a film; (ii) an insulating resin layer formed on each of a front face of the film and a rear face of the film, which rear face is opposite to the front face; (iii) a front-sided wiring pattern embedded in the insulating resin layer formed on the front face of the film, and a rear-sided wiring pattern embedded in the insulating resin layer formed on the rear face of the film; and (iv) a via which is located between the front-sided wiring pattern and the rear-sided wiring pattern and serves to electrically interconnect the front-sided wiring pattern and the rear-sided wiring pattern, wherein the insulating resin layer formed on each of the front face and the rear face of the film is thicker than the film.

Abstract translation: 柔性基板包括：（i）膜; （ii）形成在所述膜的前表面和所述膜的后表面中的每一个上的绝缘树脂层，所述后表面与所述前表面相对; （iii）嵌入到形成在所述膜前表面上的所述绝缘树脂层中的正面布线图案和嵌入在所述膜背面形成的所述绝缘树脂层中的背面布线图案; 以及（iv）位于前侧布线图案和背面布线图案之间的通孔，用于将前侧布线图案和背面布线图案电连接，其中形成在每个布线图案上的绝缘树脂层 的膜的前表面和后表面比膜厚。