公开(公告)号：US08179158B2

公开(公告)日：2012-05-15

申请号：US12552017

申请日：2009-09-01

Applicant: Peter Flamm

Inventor： Peter Flamm

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H04L25/0278 ,  H04L25/028 ,  H05K1/0246 ,  H05K1/025 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2201/10689

Abstract: Printed circuit board having a termination of a T-shaped signal line having at least two line ends, one line end being terminated using a terminating resistor against a supply voltage, and the other line end being terminated against the reference potential of the supply voltage.

Abstract translation: 印刷电路板具有具有至少两个线端的T形信号线的终端，一个线端使用针对电源电压的终端电阻终止，另一个线端抵抗电源电压的参考电位而终止。

公开(公告)号：US08071989B2

公开(公告)日：2011-12-06

申请号：US12621529

申请日：2009-11-19

Applicant: Tzu-Hao Chao

Inventor： Tzu-Hao Chao

IPC: H01L29/205

CPC classification number: H05K1/181 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09254 ,  H05K2201/09409 ,  H05K2201/10106 ,  Y02P70/611 ,  H01L2924/00

Abstract: A circuit structure of a package carrier including a plurality of chip pads, a first electrode, a second electrode, a third electrode and a fourth electrode is provided. These chip pads are arranged in an M×N array. A first bonding pad, a second bonding pad, a third bonding pad and a fourth bonding pad are disposed clockwise in the peripheral area of each chip pad in sequence. The orientations of each of the first, second, third, and fourth bonding pads of the (S−1)th row rotated by 90 degrees are equal to the orientations of each of the first, second, third and fourth bonding pads of the Sth row, respectively. The first electrode is connected with each first bonding pad. The second electrode is connected with each second bonding pad. The third electrode is connected with each third bonding pad. The fourth electrode is connected with each fourth bonding pad.

Abstract translation: 提供了包括多个芯片焊盘，第一电极，第二电极，第三电极和第四电极的封装载体的电路结构。 这些芯片焊盘以M×N阵列排列。 第一接合焊盘，第二接合焊盘，第三接合焊盘和第四接合焊盘顺序地设置在每个芯片焊盘的外围区域中。 第（S-1）行的第一，第二，第三，第四和第四接合焊盘的旋转90度的取向与Sth的第一，第二，第三和第四接合焊盘的取向相等 行。 第一电极与每个第一接合焊盘连接。 第二电极与每个第二接合焊盘连接。 第三电极与每个第三接合焊盘连接。 第四电极与每个第四接合焊盘连接。

公开(公告)号：US20110254024A1

公开(公告)日：2011-10-20

申请号：US13118575

申请日：2011-05-31

Applicant: Tzu-Hao Chao

Inventor： Tzu-Hao Chao

IPC: H01L27/15

CPC classification number: H05K1/181 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09254 ,  H05K2201/09409 ,  H05K2201/10106 ,  Y02P70/611 ,  H01L2924/00

Abstract: A multi-chip package comprises a plurality of chip pads and a plurality of LED chips. The chip pads are arranged in an M×N array, M and N each a positive integer greater than 1. A peripheral area of each chip pad comprises a respective first bonding pad, a respective second bonding pad, and a respective third bonding pad arranged in sequence in a clockwise direction. A first orientation of the respective first to third bonding pads in a first row of the N rows differs from a second orientation of the respective first to third bonding pads in a second row of the N rows by 90 degrees. Each of the LED chips is disposed on a respective one of the chip pads and electrically connected to two of the respective first to third bonding pads on a same side of the respective LED chip.

Abstract translation: 多芯片封装包括多个芯片焊盘和多个LED芯片。 芯片焊盘布置成M×N阵列，M和N各自为大于1的正整数。每个芯片焊盘的外围区域包括相应的第一焊盘，相应的第二焊盘和相应的第三焊盘， 顺时针方向。 N行的第一行中的相应的第一至第三接合焊盘的第一取向与N行的第二行中的相应的第一至第三接合焊盘的第二取向不同，90度。 每个LED芯片设置在相应的一个芯片焊盘上，并且在相应的LED芯片的同一侧上电连接到相应的第一至第三焊盘中的两个。

公开(公告)号：US08018046B2

公开(公告)日：2011-09-13

申请号：US12389456

申请日：2009-02-20

Applicant: Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

Inventor： Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

IPC: H01L23/12 ,  H05K1/00 ,  H05K7/00

CPC classification number: H01R9/09 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/0256 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/184 ,  H05K3/241 ,  H05K3/382 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/0594 ,  Y10T29/49155 ,  Y10T29/49194 ,  Y10T428/31504

Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.

Abstract translation: 一种印刷电路板，包括芯基板，形成在所述芯基板上并包括第一绝缘层的堆积层，形成在所述第一绝缘层上的导体层和形成在所述导体层上的第二绝缘层，以及一个或 在第一绝缘层上形成更多的布线图案。 导体层包括导体部分，并且导体部分分别具有跨越布线图案彼此面对的切口部分。

公开(公告)号：US20110102075A1

公开(公告)日：2011-05-05

申请号：US12985990

申请日：2011-01-06

Applicant: Steve Weir ,  Scott McMorrow

Inventor： Steve Weir ,  Scott McMorrow

IPC: H01L25/00

CPC classification number: H05K1/141 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/19105 ,  H01L2924/3011 ,  H03H7/01 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/0263 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/049 ,  H05K2201/09254 ,  H05K2201/09309 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49128 ,  Y10T29/4913

Abstract: A power distribution system for integrated circuits includes methods to damp resonance between a bypass capacitor network and a power/ground cavity of the printed circuit board that (a) does not require excessive quantities of bypass/damping components or (b) does not require high plane cavity capacitance or in the alternative can insure a Q of less than 1.4 at the transition from the bypass network to the plane cavity impedance cross-over.

Abstract translation: 用于集成电路的配电系统包括阻止旁路电容器网络和印刷电路板的电源/接地腔之间的谐振的方法，（a）不需要过量的旁路/阻尼部件，或（b）不需要高 平面腔电容，或者在旁路网络到平面腔阻抗交叉的过渡中，可以确保小于1.4的Q。

公开(公告)号：US07928543B2

公开(公告)日：2011-04-19

申请号：US12417670

申请日：2009-04-03

Applicant: Dong-Han Kim

Inventor： Dong-Han Kim

IPC: H01L23/495

CPC classification number: H01L23/4985 ,  H01L23/552 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01079 ,  H05K1/0216 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/09254 ,  H05K2201/09781 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.

Abstract translation: 带状布线基板可以具有分散布线图案。 可以在输入/输出布线图案组之间设置色散布线图案，以补偿它们之间的间隔。 连接布线图案可以被配置为将色散布线图案连接到相邻输入/输出布线图案的第一端。

公开(公告)号：US07923644B2

公开(公告)日：2011-04-12

申请号：US12611261

申请日：2009-11-03

Applicant: Jun Ishii ,  Toshiki Naitou ,  Mitsuru Honjo

Inventor： Jun Ishii ,  Toshiki Naitou ,  Mitsuru Honjo

IPC: H05K1/00

CPC classification number: H05K3/4685 ,  G11B5/484 ,  G11B5/486 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0265 ,  H05K1/056 ,  H05K3/06 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2203/0323 ,  Y10T29/49155

Abstract: A printed circuit board and method of manufacturing the printed circuit board, including a first and a second write wiring patterns, an end of a first line and an end of a second line of the first write wiring pattern are arranged on both sides of a third line of the second write wiring pattern. Circular connection portions are provided at the ends of the first line and the second line. In addition, through holes are formed in respective portions of a base insulating layer below the connection portions. Each connection portion comes in contact with a connecting region of a suspension body within the through hole.

Abstract translation: 印刷电路板和制造印刷电路板的方法，包括第一和第二写入布线图案，第一线的末端和第一写入布线图案的第二条线的末端布置在第三布线图案的两侧 第二行写线路图。 圆形连接部设置在第一线和第二线的端部。 此外，在连接部分下方的基底绝缘层的各个部分中形成通孔。 每个连接部分与通孔内的悬架体的连接区域接触。

公开(公告)号：US20110068878A1

公开(公告)日：2011-03-24

申请号：US12851393

申请日：2010-08-05

Applicant: Steve Weir ,  Scott McMorrow

Inventor： Steve Weir ,  Scott McMorrow

IPC: H03H7/38 ,  H05K1/16

CPC classification number: H05K1/141 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/0263 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/049 ,  H05K2201/09254 ,  H05K2201/09309 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T307/492

Abstract: A power distribution system for integrated circuits includes methods to damp resonance between a bypass capacitor network and a power/ground cavity of the printed circuit board that (a) does not require excessive quantities of bypass/damping components or (b) does not require high plane cavity capacitance or in the alternative can insure a Q of less than 1.4 at the transition from the bypass network to the plane cavity impedance cross-over.

公开(公告)号：US20100315684A1

公开(公告)日：2010-12-16

申请号：US12801361

申请日：2010-06-04

Applicant: Hiromasa Koike

Inventor： Hiromasa Koike

IPC: G06F15/00 ,  H04N1/38

CPC classification number: H05K1/0231 ,  H04N2201/0094 ,  H05K1/0227 ,  H05K1/0234 ,  H05K2201/09254 ,  H05K2201/09663 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: An information processing device including a printed circuit board, to access a detachable storage medium, including a control device, provided on the printed circuit board, to control access to the storage medium; a slot connector, provided on the printed circuit board to accept the storage medium; a junction portion between the storage medium and the printed circuit board, to receive a signal from the storage medium; a signal line connected between the junction portion and the control device, to transmit a signal from the storage medium to the control device; a noise line connected between the junction portion and a ground terminal, to transmit noise from the junction portion to the ground terminal; and a noise absorption element, provided in the noise line between the junction portion and the ground terminal.

Abstract translation: 一种信息处理装置，包括印刷电路板，用于访问设置在印刷电路板上的包括控制装置的可拆卸存储介质，以控制对存储介质的访问; 插槽连接器，设置在印刷电路板上以接受存储介质; 存储介质和印刷电路板之间的接合部分，用于接收来自存储介质的信号; 连接在所述接合部和所述控制装置之间的信号线，用于将信号从所述存储介质发送到所述控制装置; 连接在接合部和接地端子之间的噪声线，用于将噪声从接合部分传输到接地端子; 以及设置在接合部和接地端子之间的噪声线路中的噪声吸收元件。

公开(公告)号：US20100307807A1

公开(公告)日：2010-12-09

申请号：US12757157

申请日：2010-04-09

Applicant: Kota NODA ,  Tsutomu Yamauchi ,  Satoru Kawai

Inventor： Kota NODA ,  Tsutomu Yamauchi ,  Satoru Kawai

IPC: H05K1/02 ,  H01R43/16

CPC classification number: H05K1/115 ,  H05K1/0269 ,  H05K3/0032 ,  H05K3/0038 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/09254 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2201/09918 ,  H05K2203/0554 ,  H05K2203/1572 ,  H05K2203/166

Abstract: A method for manufacturing a double-sided circuit board includes preparing a substrate having the first and second surfaces, forming a first hole having a first opening with a diameter R1 on the first surface of the substrate, forming a second hole having a second opening with a diameter R2 on the second surface of the substrate, forming a third hole having a diameter smaller than R1 and/or R2 and connecting the first and second holes such that a penetrating hole formed of the first hole, the second hole and the third hole is formed in the substrate, forming a first conductive circuit on the first surface of the substrate, forming a second conductive circuit on the second surface of the substrate, and filling the penetrating hole with conductive material such that a through-hole conductor electrically connecting the first conductive circuit and the second conductive circuit is formed.

Abstract translation: 一种制造双面电路板的方法包括制备具有第一和第二表面的基板，在基板的第一表面上形成具有直径为R1的第一开口的第一孔，形成具有第二开口的第二孔， 在所述基板的第二表面上的直径R2，形成直径小于R1和/或R2的第三孔，并且连接所述第一孔和所述第二孔，使得由所述第一孔，所述第二孔和所述第三孔形成的穿透孔 形成在基板上，在基板的第一表面上形成第一导电电路，在基板的第二表面上形成第二导电电路，并用导电材料填充该贯穿孔，使得通孔导体将 形成第一导电电路和第二导电电路。