公开(公告)号：US20140182916A1

公开(公告)日：2014-07-03

申请号：US14064951

申请日：2013-10-28

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yee Na SHIN ,  Seung Eun LEE ,  Yul Kyo CHUNG ,  Doo Hwan LEE

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K1/115 ,  H01L2224/04105 ,  H01L2224/2518 ,  H05K1/185 ,  H05K3/421 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09854 ,  H05K2201/10636 ,  H05K2203/1469 ,  Y02P70/611 ,  Y10T29/49139

Abstract: The present invention relates to a circuit board, which can miniaturize a conductor pattern formed around a via and improve current pass characteristics of the via at the same time by including a via passing through an insulating layer to be in contact with an upper conductor pattern and a lower conductor pattern and having a bent portion whose cross-sectional area or diameter changes discontinuously.

Abstract translation: 电路板本发明涉及一种电路板，其可以使形成在通孔周围的导体图案小型化，同时通过包括与上导体图案接触的绝缘层的通孔，同时改善通孔的电流通过特性， 下导体图案并具有弯曲部分，其横截面积或直径不连续地变化。

公开(公告)号：US08742499B2

公开(公告)日：2014-06-03

申请号：US12608751

申请日：2009-10-29

Applicant: Shizuki Nakajima ,  Hiroyuki Nagai ,  Yuji Shirai ,  Hirokazu Nakajima ,  Chushiro Kusano ,  Yu Hasegawa ,  Chiko Yorita ,  Yasuo Osone

Inventor： Shizuki Nakajima ,  Hiroyuki Nagai ,  Yuji Shirai ,  Hirokazu Nakajima ,  Chushiro Kusano ,  Yu Hasegawa ,  Chiko Yorita ,  Yasuo Osone

IPC: H01L27/082 ,  H01L27/088 ,  H01L21/8222 ,  H01L29/78

CPC classification number: H01L29/7835 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/66 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L27/088 ,  H01L29/04 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/41758 ,  H01L29/66659 ,  H01L29/7371 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05171 ,  H01L2224/05553 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10161 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/0206 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/01032 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/013

Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.

Abstract translation: 在其中形成用于功率放大器模块的功率放大器电路的LDMOSFET元件形成的半导体芯片中，源极突起电极设置在LDMOSFET形成区域中，其中多个源极区域，多个漏极区域和多个栅极 形成用于LDMOSFET元件的电极。 源极突起电极通过源极导体层形成在主要由铝制成的源极焊盘上，该源极导体层比源焊盘厚，主要由铜制成。 在源凸起电极和源极导体层之间不设置树脂膜。

公开(公告)号：US08714763B2

公开(公告)日：2014-05-06

申请号：US13381705

申请日：2010-06-15

Applicant: Yasumori Kuromizu

Inventor： Yasumori Kuromizu

IPC: G09F13/04

CPC classification number: G02F1/133603 ,  G02F2001/133612 ,  H05K1/142 ,  H05K3/0061 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10106 ,  H05K2201/10287 ,  H05K2201/10356

Abstract: The present invention aims at providing a lighting device configured to suppress uneven brightness, and a display device or a television receiver which includes the lighting device. The lighting device of the present invention includes a plurality of LEDs 16, an LED board 17S, a chassis 14, a connecting component 60, and a reflection sheet 21. The LEDs 16 are mounted on the LED board 175. Both of the LED boards 17S and 17C are attached to the chassis 14. The connecting component 60 electrically connect the LED boards 17S and 17C to each other. The reflection sheet 21 is overlaid on light source mounted surfaces 17A. In the lighting device, the connecting component 60 is arranged on a connecting component attached surface 17B of the LED board 17S. The connecting component attached surface 17B is opposite to the surface on which the reflection sheet 21 is overlaid.

Abstract translation: 本发明旨在提供一种被配置为抑制不均匀亮度的照明装置，以及包括该照明装置的显示装置或电视接收机。 本发明的照明装置包括多个LED16，LED板17S，底座14，连接部件60和反射片21.LED16安装在LED板175上。两个LED板 17S和17C连接到底盘14.连接部件60将LED板17S和17C彼此电连接。 反射片21覆盖在光源安装表面17A上。 在照明装置中，连接部件60配置在LED基板17S的连接部件安装面17B上。 连接部件安装面17B与反射片21重叠的面相反。

公开(公告)号：US20140043782A1

公开(公告)日：2014-02-13

申请号：US14058863

申请日：2013-10-21

Applicant: HSIO TECHNOLOGIES, LLC

Inventor： James Rathburn

IPC: H01L23/522 ,  H05K3/40

CPC classification number: H01L23/34 ,  G01R1/0416 ,  H01L23/522 ,  H01L2224/13 ,  H05K3/325 ,  H05K3/4007 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/09036 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/10378 ,  H05K2203/162 ,  Y10T29/49165

Abstract: An electrical interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of first conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the first conductive traces into the openings. Vias extending through the substrate are electrically coupled the first conductive traces. A plurality of second conductive traces extend along the second surface of the substrate and are electrically coupled to a vias. The second conductive traces are configured to electrical couple with the contact pads on the PCB.

Abstract translation: IC器件上的端子和印刷电路板（PCB）上的接触焊盘之间的电气互连。 电互连包括具有第一表面的基板，该第一表面具有多个开口，其布置成对应于IC器件上的端子。 柔性材料位于开口中。 多个第一导电迹线沿着衬底的第一表面延伸到柔性材料上。 柔性材料提供抵抗第一导电迹线弯曲到开口中的偏压力。 延伸穿过衬底的通孔电耦合第一导电迹线。 多个第二导电迹线沿着衬底的第二表面延伸并且电耦合到通孔。 第二导电迹线被配置为与PCB上的接触焊盘电耦合。

公开(公告)号：US20140004720A1

公开(公告)日：2014-01-02

申请号：US14016398

申请日：2013-09-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Kai Yao ,  Yongfa Zhu ,  Yingpei Huang

IPC: H05K1/11

CPC classification number: H05K1/117 ,  H05K1/0265 ,  H05K1/0298 ,  H05K3/4046 ,  H05K2201/0919 ,  H05K2201/09481 ,  H05K2201/0979 ,  H05K2201/10416

Abstract: A golden finger and a board edge interconnecting device are disclosed. The golden finger includes a printed circuit board (PCB) surface layer and at least one PCB inner layer, where a metal foil of the PCB inner layer is connected to a metal foil of the PCB surface layer through a current-carrying structure, so that a current-carrying channel of the golden finger passes through the PCB surface layer and the PCB inner layer. The board edge interconnecting device includes the foregoing golden finger. In the embodiments, a current-carrying capacity of a PCB in the golden finger is increased without increasing a size and thickness of a copper foil of the PCB in the golden finger, thereby effectively improving the current-carrying capacity of the PCB in the golden finger.

Abstract translation: 公开了金手指和板边缘互连装置。 金手指包括印刷电路板（PCB）表面层和至少一个PCB内层，其中PCB内层的金属箔通过载流结构连接到PCB表面层的金属箔，使得 金手指的载流通道穿过PCB表面层和PCB内层。 板边缘互连装置包括上述金手指。 在实施例中，金手指上的PCB的载流能力增加，而不增加金手指中PCB的铜箔的尺寸和厚度，从而有效地提高了黄金中PCB的载流能力 手指。

公开(公告)号：US08519271B2

公开(公告)日：2013-08-27

申请号：US12485615

申请日：2009-06-16

Applicant: Harutoshi Oikawa ,  Kiyohiro Kimura

Inventor： Harutoshi Oikawa ,  Kiyohiro Kimura

IPC: H05K1/00

CPC classification number: H05K3/361 ,  H05K3/281 ,  H05K3/323 ,  H05K3/421 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/097 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2203/1572

Abstract: A flexible printed circuit includes: a flexible substrate extending from a first end section to a second end section, and having an opening or a notch in proximity to the first end section; a first wiring layer extending from the first end section to the second end section so as to avoid the opening or the notch; a second wiring layer extending from the first end section to the second end section so as to block the opening or the notch; a first conductive member being formed opposed to the flexible substrate in relation to the first wiring layer and at least in proximity to the first end section in a region opposed to the first wiring layer, and being electrically connected to the first wiring layer; and a second conductive member electrically connected to the second wiring layer via the opening or the notch.

Abstract translation: 柔性印刷电路包括：柔性基板，其从第一端部延伸到第二端部，并且具有靠近第一端部的开口或凹口; 第一布线层，从第一端部延伸到第二端部，以避免开口或凹口; 第二布线层，其从所述第一端部延伸到所述第二端部，以阻挡所述开口或所述凹口; 第一导电构件，其与所述柔性基板相对于所述第一布线层形成，并且在与所述第一布线层相对的区域中至少靠近所述第一端部，并且电连接到所述第一布线层; 以及通过所述开口或所述凹口与所述第二布线层电连接的第二导电构件。

公开(公告)号：US08479388B2

公开(公告)日：2013-07-09

申请号：US12207713

申请日：2008-09-10

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01K3/10

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

Abstract translation: 一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入件的方法。 插入件在横截面中具有半环形结构，并由介电弹性体材料构成。 多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触 飞机

公开(公告)号：US08455770B2

公开(公告)日：2013-06-04

申请号：US13196129

申请日：2011-08-02

Applicant: Junichi Nakamura ,  Yuji Kobayashi

Inventor： Junichi Nakamura ,  Yuji Kobayashi

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/116 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3473 ,  H05K3/4007 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/09509 ,  H05K2203/0338 ,  H05K2203/0361 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of fabricating a wiring board includes forming a resist layer, such as a solder or plating resist layer, defining an opening portion on a support board such that a portion of the support board is exposed. An electrode is formed directly on the support board within the opening portion, and the plating resist layer, when used, is removed. An insulating layer is formed on the electrode, as well as the support board or solder resist layer, and a wiring portion connected to the electrode at the insulating layer is also formed. A solder resist layer having an opening portion is then formed on the wiring portion, and the support board is removed to expose a surface of the electrode or a surface of the electrode and insulating layer. Another solder resist layer having an opening portion may then be formed on the exposed surface of the insulating layer.

Abstract translation: 制造布线板的方法包括在支撑板上形成限定开口部分的焊料或电镀抗蚀剂层的抗蚀剂层，使得支撑板的一部分露出。 电极直接形成在开口部内的支撑板上，当使用时，电镀抗蚀剂层被去除。 在电极以及支撑板或阻焊层上形成绝缘层，并且还形成连接到绝缘层处的电极的布线部分。 然后在布线部分上形成具有开口部分的阻焊层，并且去除支撑板以暴露电极的表面或电极和绝缘层的表面。 然后可以在绝缘层的暴露表面上形成具有开口部分的另一阻焊层。

公开(公告)号：US20130118791A1

公开(公告)日：2013-05-16

申请号：US13734474

申请日：2013-01-04

Applicant: FUJIKURA LTD.

Inventor： Masahiro OKAMOTO

IPC: H05K1/18 ,  H05K3/32

CPC classification number: H05K1/183 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2924/15153 ,  H01L2924/19105 ,  H05K1/186 ,  H05K3/321 ,  H05K3/4623 ,  H05K2201/09481 ,  Y10T29/4913

Abstract: A laminated wiring board, includes: a first substrate in which a conductor circuit is formed on one surface of an insulating layer and an adhesive layer is formed on an other surface of the insulating layer, and conductors are formed in via holes that pass through the insulating layer and the adhesive layer so that the conductor circuit is partially exposed therefrom; an electronic component electrically connected to the conductor circuit by allowing electrodes of the electronic component to be connected to the conductors; an embedding member arranged around the electronic components so that the electronic component is embedded therein; and a second substrate having an adhesive layer laminated to face the adhesive layer of the first substrate and sandwich the electronic component and the embedding member, wherein each of the electrodes of the electronic component is continuous with the conductor circuit through two or more of the conductors.

Abstract translation: 一种叠层电路板，包括：在绝缘层的一个表面上形成导体电路并在绝缘层的另一个表面上形成粘合层的第一基板，并且在通孔中形成导体， 绝缘层和粘合剂层，使得导体电路部分地暴露于其中; 通过允许电子部件的电极连接到导体而与导体电路电连接的电子部件; 嵌入构件，其围绕电子部件布置，使得电子部件嵌入其中; 以及第二基板，其具有层压以面对第一基板的粘合剂层并夹持电子部件和嵌入部件的粘合剂层，其中电子部件的每个电极通过两个或更多个导体与导体电路连续 。

公开(公告)号：US08368846B2

公开(公告)日：2013-02-05

申请号：US13052302

申请日：2011-03-21

Applicant: Gi-Cherl Kim ,  Se-Ki Park ,  Ju-Young Yoon ,  Byung-Choon Yang ,  Seok-Hyun Nam ,  Sang-Yu Lee

Inventor： Gi-Cherl Kim ,  Se-Ki Park ,  Ju-Young Yoon ,  Byung-Choon Yang ,  Seok-Hyun Nam ,  Sang-Yu Lee

IPC: G02F1/1333 ,  G02F1/1335

CPC classification number: H05K1/0203 ,  G02F1/133603 ,  G02F2001/133607 ,  H01L33/58 ,  H01L33/62 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49107 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/1815 ,  H01L2924/19041 ,  H05K3/445 ,  H05K2201/09481 ,  H05K2201/10106 ,  H05K2201/10553 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00011 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A two-dimensional light source includes a base substrate having holes, wires disposed on a lower surface of the base substrate, a light emitting diode (LED) chip disposed on an upper surface of the base substrate, plugs that connect two electrodes of the LED chip to the wires through the holes, a buffer layer covering the LED chip, and an optical layer that is disposed on the buffer layer and has an optical pattern formed at a portion of the optical layer corresponding to the LED chip.

Abstract translation: 二维光源包括具有孔的基底基板，设置在基底基板的下表面上的布线，设置在基底基板的上表面上的发光二极管（LED）芯片，连接LED的两个电极的插头 通过孔穿过导线，覆盖LED芯片的缓冲层，以及设置在缓冲层上并具有形成在对应于LED芯片的光学层的一部分的光学图案的光学层。