公开(公告)号：US20040200801A1

公开(公告)日：2004-10-14

申请号：US09989898

申请日：2001-11-19

Inventor： Laurence M.C. Lai ,  Anthony Russell ,  Michael J. Shaw

IPC: H01B013/00 ,  H04R001/00 ,  H04R009/06 ,  H04R011/02

CPC classification number: H05K1/0265 ,  B32B15/04 ,  C23F1/02 ,  H04R7/04 ,  H04R31/003 ,  H05K1/09 ,  H05K1/165 ,  H05K3/06 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/098 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10T428/10 ,  Y10T428/24 ,  Y10T428/24917 ,  Y10T428/31678

Abstract: To achieve a large thickness of conductive metal-containing material in a feature of a product unit processed with a liquid-based etch process, the desired thickness of material is apportioned to the two opposing surfaces of a substrate to create a two-part feature. Conventional features are made by identically patterning two same-thickness metal-containing layers and electrically connecting the resulting patterned parts in any suitable manner. However, features may also be made that do not have identical parts on opposite sides of the substrate, the two parts being electrically connected but differing in thickness, in shape, or both. Moreover, having two metal-containing layers separated by an insulator is also useful for allowing different sections of the same feature or circuit to cross one another without shorting, or to overlap in whole or in part without shorting.

Abstract translation: 为了在用基于液体的蚀刻工艺处理的产品单元的特征中实现大厚度的含导电金属的材料，将所需的材料厚度分配给基板的两个相对的表面以产生两部分特征。 传统的特征是通过相同地构图两个相同厚度的含金属层并以任何合适的方式电连接所得到的图案化部分。 然而，也可以在衬底的相对侧上不具有相同部件的特征，两个部分电连接但是厚度，形状或两者均不同。 此外，具有由绝缘体隔开的两个含金属层也可用于允许相同特征或电路的不同部分彼此交叉而不短路，或者在不短路的情况下全部或部分重叠。

公开(公告)号：US20040131832A1

公开(公告)日：2004-07-08

申请号：US10713390

申请日：2003-11-14

Inventor： Nobuyoshi Tsukaguchi ,  Masami Kimura

IPC: B32B003/00

CPC classification number: H01L23/3735 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/244 ,  H05K3/38 ,  H05K2201/0355 ,  H05K2201/098 ,  Y10T428/12576 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

Abstract: There is provided a metal/ceramic circuit board capable of eliminating discrepancy during mounting of parts to improve the reliability of mounting of the parts. The metal/ceramic circuit board has a ceramic substrate 10, and a metal circuit plate (a copper plate 14) bonded to the ceramic substrate 10, the metal circuit plate having a thickness which is more than 0.25 mm and which is less than 0.3 mm, and the metal circuit plate having a skirt spreading length (a dimensional difference between the bottom and top portion of the peripheral edge portion of the metal circuit plate) of less than 50 nullm.

Abstract translation: 提供了一种金属/陶瓷电路板，其能够在安装零件期间消除差异，以提高部件安装的可靠性。 金属/陶瓷电路板具有陶瓷基板10和与陶瓷基板10接合的金属电路板（铜板14），金属电路板的厚度大于0.25mm且小于0.3mm ，并且金属电路板具有小于50μm的裙部扩展长度（金属电路板的周边边缘部分的底部和顶部之间的尺寸差）。

公开(公告)号：US20040113725A1

公开(公告)日：2004-06-17

申请号：US10322157

申请日：2002-12-17

Inventor： Qing Ma ,  Joseph Hayden III ,  Tsung-Kuan Allen Chou ,  Quan Tran

IPC: H01P003/08

CPC classification number: H01P11/003 ,  H01P3/003 ,  H05K1/0219 ,  H05K1/0237 ,  H05K3/243 ,  H05K2201/09236 ,  H05K2201/09736 ,  H05K2201/098

Abstract: Coplanar waveguides have a center signal line and a pair of ground lines on either side formed of a sputtered material such as gold (Au). Such waveguides are subject to what is known as the edge effect at high frequency operation causing currents to concentrate and flow along adjacent edges of the lines. Providing a thicker plated layer only on adjacent edges of the lines provide substantial performance improvements over sputtered lines alone while saving significant amount of Au, thus reducing costs.

Abstract translation: 共平面波导具有中心信号线和由诸如金（Au）的溅射材料形成的任一侧上的一对接地线。 这种波导在高频操作下受到所谓的边缘效应的影响，导致电流集中并沿着线的相邻边缘流动。 仅在线路的相邻边缘上提供较厚的镀层仅提供了超过溅射线的显着性能改善，同时节省了大量的Au，从而降低了成本。

公开(公告)号：US06750132B2

公开(公告)日：2004-06-15

申请号：US10088479

申请日：2002-03-20

Applicant: Kenji Morimoto ,  Hiroshi Ochi

Inventor： Kenji Morimoto ,  Hiroshi Ochi

IPC: H01L2144

CPC classification number: H01L24/16 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13016 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/45144 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/3025 ,  H05K1/092 ,  H05K1/111 ,  H05K3/02 ,  H05K3/321 ,  H05K2201/0367 ,  H05K2201/098 ,  H05K2201/10674 ,  H05K2203/0514 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/05599

Abstract: According to the present invention, when a semiconductor element having protruding electrodes formed thereon is connected to a circuit board via conductive resin, stable connection is made even when an electrode pitch is small on the semiconductor element. On semiconductor element package regions on the circuit board, a paste electrode material containing photopolymerizable materials is printed to form a film having a prescribed thickness, and this electrode material film is baked after exposure and development thereof so as to obtain circuit electrodes having edges warped in a direction of going apart from the circuit board surface. Then, the protruding electrodes and the concave surfaces of the circuit electrodes are brought in abutment with each other and connected via the conductive resin which surrounds the abutments between the respective electrodes and is held on the concave surfaces of the circuit electrodes. With this arrangement, the concave surfaces of the circuit electrodes act as saucers and prevent the conductive resin from being squeezed out, thereby eliminating possible occurrence of short circuits.

公开(公告)号：US06600404B1

公开(公告)日：2003-07-29

申请号：US09228971

申请日：1999-01-12

Applicant: Takashi Kajino

Inventor： Takashi Kajino

IPC: H01F500

CPC classification number: H05K1/0265 ,  H01F5/003 ,  H01F17/0006 ,  H01F17/0013 ,  H01F19/04 ,  H05K1/165 ,  H05K3/062 ,  H05K3/108 ,  H05K2201/098

Abstract: A planar coil including and insulating substrate, and a coil conductive filament having a thickness of 20 to 400 &mgr;m and formed on at least one surface of the insulating substrate, the coil conductive filament having a gap whose aspect ratio (H/G) is at least 1. The coil conductive filament has a cross-section in a substantially mushroom shape having a head and a neck, the head has a width (L) which is a least twice as large as a width (l) of the neck thereof, at most 1.5 times as large as a height of the head, and at least twice as large as a minimum spacing (G) between adjacent coil conductive filaments.

Abstract translation: 包括绝缘基板的平面线圈和形成在绝缘基板的至少一个表面上的厚度为20〜400μm的线圈导电丝，线圈导电丝具有纵横比（H / G）为 线圈导电细丝具有基本上为蘑菇状的横截面，具有头部和颈部，头部的宽度（L）为其颈部的宽度（l）的至少两倍， 至多为头部高度的1.5倍，并且至少是相邻线圈导电细丝之间的最小间距（G）的两倍。

公开(公告)号：US06469259B2

公开(公告)日：2002-10-22

申请号：US09795765

申请日：2001-02-27

Applicant: Yoshihiro Takeshita ,  Shinya Terao ,  Satoru Takenouchi ,  Masaki Kaji ,  Ryuji Koga

Inventor： Yoshihiro Takeshita ,  Shinya Terao ,  Satoru Takenouchi ,  Masaki Kaji ,  Ryuji Koga

IPC: H01R1204

CPC classification number: H05K1/0234 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/0224 ,  H05K1/0298 ,  H05K1/167 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/098 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A wiring board of the present invention readily controls a power source voltage and unwanted irradiation noises developed across a power source layer and a ground layer over a broad range of frequencies with a simple arrangement. The wiring board has an on-board surface on the surface of a dielectric substrate, on which a semiconductor device or the like is mounted, and a power source layer and a ground layer, which are made of a conductor material principally composed of at least one kind of element selected from Cu, W, and Mo, are provided on the back surface of the dielectric substrate or within the same. The periphery of at least one of low resistance areas of the power source layer and ground layer, respectively is provided with a corresponding high resistance area having a higher sheet resistance than that of the respective low resistance areas.

Abstract translation: 本发明的布线基板通过简单的布置容易地控制在宽频率范围内在电源层和接地层两端产生的电源电压和不期望的照射噪声。 布线基板在其上安装有半导体器件等的电介质基板的表面上具有板状表面，电源层和接地层由导体材料制成，主要由至少包括 在电介质基板的背面或其内部设置选自Cu，W和Mo中的一种元素。 电源层和接地层的至少一个低电阻区域的周边分别设置有相对于各个低电阻区域的薄层电阻高的相应的高电阻区域。

公开(公告)号：US06266016B1

公开(公告)日：2001-07-24

申请号：US09686637

申请日：2000-10-11

Applicant: Leif Bergstedt ,  Spartak Georgian

Inventor： Leif Bergstedt ,  Spartak Georgian

IPC: H01Q138

CPC classification number: H01P3/084 ,  H01Q9/0407 ,  H01Q9/045 ,  H01Q13/206 ,  H01Q21/0081 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2201/09972

Abstract: The invention relates to a microstrip arrangement comprising a first and a second microstrip conductor. The two microstrip conductors have essentially the same dimensions in their longitudinal direction and transverse direction, and are galvanically interconnected by means of at least one connection. The two microstrip conductors also extend essentially parallel to one another on either side of a dielectric material. As a result of this design of the microstrip arrangement, the field losses and also other influences caused by the dielectric material will be very considerably reduced, and in practice a resultant microstrip arrangement is obtained, which, with regard to its electrical performance, appears to be suspended in the air. Preferred embodiments comprise a microstrip antenna, a circuit board and a conductor application.

Abstract translation: 本发明涉及一种包括第一和第二微带导体的微带布置。 两个微带导体在其纵向和横向上具有基本上相同的尺寸，并且通过至少一个连接电流互连。 两个微带导体也在电介质材料的任一侧基本上彼此平行地延伸。 作为这种微带布置设计的结果，由介电材料引起的场损耗和其它影响将会非常显着地降低，并且在实践中获得了微结构的微结构，对于其电性能来说， 悬挂在空中。 优选实施例包括微带天线，电路板和导体应用。

公开(公告)号：US5904863A

公开(公告)日：1999-05-18

申请号：US848312

申请日：1997-04-30

Applicant: Michael M. Hatfield ,  Marshall I. Gurian

Inventor： Michael M. Hatfield ,  Marshall I. Gurian

IPC: C03C15/00 ,  C03C17/06 ,  G03F7/40 ,  H05K3/06 ,  B44C1/22

CPC classification number: H05K3/067 ,  C03C15/00 ,  C03C17/06 ,  G03F7/40 ,  C03C2218/33 ,  H05K2201/098 ,  H05K2203/1476 ,  H05K3/064

Abstract: A process for etching the sides of a trace remove the feet which extend laterally out from the sides and over a circuit board substrate adjacent the trace.

Abstract translation: 用于蚀刻迹线的侧面的方法去除从侧面横向延伸并且在与迹线相邻的电路板基板上的脚部。

公开(公告)号：US5483105A

公开(公告)日：1996-01-09

申请号：US233025

申请日：1994-04-25

Applicant: Suryanarayana Kaja ,  Eric D. Perfecto ,  William H. Price ,  Sampath Purushothaman ,  Srinivasa N. Reddy ,  Vivek M. Sura ,  George E. White

Inventor： Suryanarayana Kaja ,  Eric D. Perfecto ,  William H. Price ,  Sampath Purushothaman ,  Srinivasa N. Reddy ,  Vivek M. Sura ,  George E. White

IPC: H01R12/32 ,  H01L23/498 ,  H01R12/04 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49811 ,  H05K1/111 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2201/09736 ,  H05K2201/098 ,  Y02P70/611

Abstract: A ceramic substrate pad used for establishing brazed connection between a pin and the substrate in the packaging of microelectronic semiconductor circuit chip. The pad is characterized by a stepped setback in the upper surface thereof which setback is oxidized to prevent wetting by the brazing alloy which bonds the pin to the pad. Stresses attributable to the brazing are isolated from the setback area and thus have reduced effect in causing cracking at the edges of the pad-substrate interface.

Abstract translation: 一种用于在微电子半导体电路芯片的封装中在引脚和衬底之间建立钎焊连接的陶瓷衬底焊盘。 该焊盘的特征在于在其上表面具有阶梯状的挫折，其挫折被氧化以防止通过将销钉固定到焊盘的钎焊合金的润湿。 由于钎焊产生的应力与塌陷区域隔离，因此在焊盘 - 衬底界面的边缘处产生破裂的效果降低。

公开(公告)号：US5403651A

公开(公告)日：1995-04-04

申请号：US168407

申请日：1993-12-17

Applicant: Masahide Miyagi

Inventor： Masahide Miyagi

IPC: H01L21/48 ,  H05K1/02 ,  H05K1/03 ,  B32B9/00

CPC classification number: H01L21/4839 ,  H05K1/0271 ,  H05K1/0201 ,  H05K1/0306 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2201/09145 ,  H05K2201/098 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: An insulating substrate for mounting semiconductor devices that is composed of a thin flat plate of inexpensive alumina (Al.sub.2 O.sub.3) preferably in the range of 0.26 to 0.29 mm in thickness. Copper foil sheets are applied to both sides of the flat plate with edges spaced a distance back from the end surface of the plate to increase air path distance between the edges of the sheets of foil applied to opposite sides of the plate. The difference in distance between the end surface of the alumina plate and the edges of each copper foil is 0.5 mm or less to balance thermal stress upon heating and cooling of semiconductors soldered to the copper foil.

Abstract translation: 一种用于安装半导体器件的绝缘衬底，其由廉价氧化铝（Al 2 O 3）的薄平板优选在0.26至0.29mm的范围内。 将铜箔片施加到平板的两侧，其边缘与板的端面间隔开一段距离，以增加施加到板的相对侧的箔片的边缘之间的空气路径距离。 氧化铝板的端面与每个铜箔的边缘之间的距离差为0.5mm以下，以平衡焊接到铜箔的半导体的加热和冷却时的热应力。