公开(公告)号：US5526974A

公开(公告)日：1996-06-18

申请号：US370631

申请日：1995-01-10

Applicant: Thomas Gordon ,  Douglas Farlow

Inventor： Thomas Gordon ,  Douglas Farlow

IPC: H05K3/30 ,  H05K13/04 ,  H05K3/34

CPC classification number: H05K13/0413 ,  H05K3/303 ,  H01L2924/181 ,  H05K2201/10204 ,  H05K2201/10689 ,  H05K2203/0195 ,  H05K2203/167 ,  Y02P70/613

Abstract: A method and kit for precisely placing fine pitch surface-mount electronic components onto printed circuit boards. An alignment substrate having a pattern of solder pads and holes or transverse edges corresponding to the pattern of solder pads and holes or edges on a printed circuit board is secured to a base by registration pins fastened to the base and inserted into contact with said holes or edges. Generally, the alignment substrate is preferably another circuit board identical with the board to be bonded to the electrical component. A template having a pattern of recesses corresponding to the component lead pattern is secured over the alignment substrate. A component is placed on the template with leads in the recesses. The component is lifted away, a printed circuit board is placed over the template and the component is lower onto the board. The board with component in place can then be removed for soldering.

Abstract translation: 一种用于将细间距表面贴装电子元件精确放置到印刷电路板上的方法和套件。 具有对应于焊盘和印刷电路板上的焊盘和孔的图形的焊盘和孔或横向边缘的对准衬底通过固定到基座并插入与所述孔接触的对准销固定到基座上， 边缘。 通常，取向基板优选为与要与电气部件接合的基板相同的另一电路基板。 具有对应于部件引线图案的凹部图案的模板被固定在对准基板上。 将部件放置在模板上，并在凹槽中引线。 将组件提起，将印刷电路板放置在模板上，并将组件放在板上。 然后可以将具有组件的板放置在适当位置以进行焊接。

公开(公告)号：US4529116A

公开(公告)日：1985-07-16

申请号：US489677

申请日：1983-04-28

Applicant: Ernst A. Gutbier

Inventor： Ernst A. Gutbier

IPC: B23K3/06 ,  G01N13/00 ,  G01N13/02 ,  H05K3/34

CPC classification number: H05K3/3468 ,  B23K3/0653 ,  G01N13/00 ,  B23K2201/42 ,  G01N2013/0225 ,  H05K2201/10204 ,  H05K2203/162

Abstract: First and second transparent metallized gauge plates (52 and 52') of solder-nonwettable, heat-resistant material, such as glass or quartz, each have a solder wave test pattern in the form of spaced parallel metal strips (56 and 56') formed thereon. The metal strips (56) on the first gauge plate (52) are of progressively increasing widths, with a narrowest strip located adjacent one edge of the plate and a widest strip located adjacent an opposite edge of the plate. The metal strips 56' on the second gauge plate (52') are of uniform widths. The first gauge plate (52) is engaged with a solder wave (34) to measure the activation level of a soldering flux (44) being introduced into the solder wave, and thereby to determine the capability of the solder wave to produce properly soldered printed circuit board assemblies (10). The second gauge plate is engaged with the solder wave (34) to measure and/or adjust other flow characteristics of the solder wave, such as a width of solder wave impingement (80 ) on the printed circuit board assemblies (10).

Abstract translation: 焊料不可润湿的耐热材料（例如玻璃或石英）的第一和第二透明金属化计量板（52和52'）各自具有间隔开的平行金属条（56和56'）形式的焊波测试图案， 形成在其上。 第一计量板（52）上的金属条（56）具有逐渐增加的宽度，最窄的带位于板的一个边缘附近，并且最宽的带位于板的相对边缘附近。 第二计量板（52'）上的金属条56'具有均匀的宽度。 第一测量板（52）与焊波（34）接合，以测量引入到焊波中的焊剂（44）的激活电平，从而确定焊波产生适当焊接的印刷 电路板组件（10）。 第二测量板与焊波（34）接合以测量和/或调整焊波的其它流动特性，例如印刷电路板组件（10）上的焊波冲击（80）的宽度。

公开(公告)号：US2911045A

公开(公告)日：1959-11-03

申请号：US49340655

申请日：1955-03-10

Applicant: RCA CORP

Inventor： WRIGHT THEODORE M

IPC: B26F1/04 ,  H05K3/00

CPC classification number: B26F1/04 ,  H05K3/0008 ,  H05K3/005 ,  H05K2201/10204 ,  Y10T83/4561 ,  Y10T83/4645

公开(公告)号：US12082346B2

公开(公告)日：2024-09-03

申请号：US18175898

申请日：2023-02-28

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Masahiro Kyozuka

IPC: H05K1/02 ,  H05K1/05 ,  H05K3/00

CPC classification number: H05K3/0011 ,  H05K1/0271 ,  H05K1/05 ,  H05K2201/093 ,  H05K2201/09372 ,  H05K2201/10204

Abstract: A wiring board includes a first insulating layer, a pad formed on one surface of the first insulating layer, a second insulating layer, formed on the one surface of the first insulating layer, and including an opening exposing the pad, and a reinforcing metal layer formed in contact with the first insulating layer, and provided around the pad so as to be separated from the pad in a plan view. The pad is disposed inside the opening without making contact with the second insulating layer. An end, on a side of the first insulating layer, in a portion of an inner side surface of the opening of the second insulating layer makes contact with the reinforcing metal layer, and an end in another portion of the inner side surface of the opening of the second insulating layer makes contact with the one surface of the first insulating layer.

公开(公告)号：US20240268034A1

公开(公告)日：2024-08-08

申请号：US18382278

申请日：2023-10-20

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jesang Park ,  Changgun Oh ,  Yangje Lee ,  Hyun Kyung Park

IPC: H05K3/10 ,  H05K1/03 ,  H05K3/46

CPC classification number: H05K3/103 ,  H05K1/0306 ,  H05K3/4697 ,  H05K2201/0212 ,  H05K2201/0753 ,  H05K2201/099 ,  H05K2201/10204 ,  H05K2203/0186 ,  H05K2203/1377

Abstract: A circuit board according to an embodiment includes: a first insulation layer, a first circuit wire that is disposed on the first insulation layer, a second insulation layer that covers the first insulation layer and the first circuit wire, and includes a material that is different from that of the first insulation layer, and a third insulation layer that is disposed on the second insulation layer and includes a cavity. A bottom surface of the cavity is a top surface of the second insulation layer.

公开(公告)号：US20190037687A1

公开(公告)日：2019-01-31

申请号：US15810295

申请日：2017-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James A. BUSBY ,  John R. DANGLER ,  Michael J. FISHER ,  David C. LONG

IPC: H05K1/02 ,  G06F21/87 ,  H05K5/02 ,  H05K1/18 ,  H05K1/11 ,  H05K1/09 ,  G01N27/04

CPC classification number: H05K1/0275 ,  G01N27/045 ,  G06F21/86 ,  G06F21/87 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K1/181 ,  H05K5/0208 ,  H05K2201/10151 ,  H05K2201/10204 ,  H05K2201/10371 ,  H05K2201/10522

Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include at least one tamper-respondent sensor and a detector. The at least one tamper-respondent sensor includes conductive lines which form, at least in part, at least one tamper-detect network of the tamper-respondent sensor(s). In addition, the tamper-respondent sensor(s) includes at least one interconnect element associated with one or more conductive lines of the conductive lines forming, at least in part, the tamper-detect network(s). The interconnect element(s) includes at least one interconnect characteristic selected to facilitate obscuring a circuit lay of the at least one tamper-detect network. In operation, the detector monitors the tamper-detect network(s) of the tamper-respondent sensor(s) for a tamper event.

公开(公告)号：US09995977B2

公开(公告)日：2018-06-12

申请号：US15318532

申请日：2015-06-19

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Masaki Nakayama ,  Motoji Shiota ,  Takashi Matsui ,  Yasuhiko Tanaka ,  Hiroki Miyazaki

IPC: G02F1/1345 ,  H05K1/18 ,  H05K1/02 ,  H01L23/498 ,  H01L23/31

CPC classification number: G02F1/13452 ,  G02F1/13454 ,  H01L23/3142 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K1/028 ,  H05K1/0306 ,  H05K1/181 ,  H05K3/305 ,  H05K3/323 ,  H05K2201/09781 ,  H05K2201/10136 ,  H05K2201/10204 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2201/10984 ,  Y02P70/613 ,  H01L2924/00

Abstract: An array circuit board 11B includes a glass substrate, an IC chip 20, two ACFs 30, and a resin film 32. The IC chip 20 is disposed on the glass substrate. The ACFs 30 are disposed between the glass substrate and the IC chip 20 for electrically connecting the glass substrate and the IC chip 20 together. The ACFs 30 are separated from each other. The resin film 32 is made of resin material having cure shrinkage smaller than the ACFs 30 and disposed to fill a gap between the ACFs 30 adjacent to each other between the glass substrate and the IC chip 20.

公开(公告)号：US09774070B2

公开(公告)日：2017-09-26

申请号：US14537059

申请日：2014-11-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Nobuo Ikemoto ,  Yuki Wakabayashi ,  Shigeru Tago

IPC: H01P3/08 ,  H01P11/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K3/36 ,  H01R12/62 ,  H05K3/00 ,  H05K3/46 ,  H01R103/00 ,  H01R24/50

CPC classification number: H01P3/082 ,  H01P3/08 ,  H01P11/003 ,  H01R12/62 ,  H01R24/50 ,  H01R2103/00 ,  H05K1/0219 ,  H05K1/0225 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0253 ,  H05K1/115 ,  H05K1/118 ,  H05K1/147 ,  H05K3/0052 ,  H05K3/363 ,  H05K3/4623 ,  H05K3/4632 ,  H05K2201/07 ,  H05K2201/09154 ,  H05K2201/0919 ,  H05K2201/09481 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/097 ,  H05K2201/09845 ,  H05K2201/10037 ,  H05K2201/10204 ,  Y10T29/49016

Abstract: In a high frequency signal line, a first signal line extends along a first dielectric element assembly, a first reference ground conductor extends along the first signal line, a second signal line is provided in or on the second dielectric element assembly and extends along the second dielectric element assembly, a second reference ground conductor is provided in or on the second dielectric element assembly and extends along the second signal line. A portion of a bottom surface at an end of the first dielectric element assembly and a portion of the top surface at an end of the second dielectric element assembly are joined together such that a joint portion of the first and second dielectric element assemblies includes a corner. The second signal line and the first signal line are electrically coupled together. The first and second reference ground conductors are electrically coupled together.

公开(公告)号：US09750129B2

公开(公告)日：2017-08-29

申请号：US15265704

申请日：2016-09-14

Applicant: Intel Corporation

Inventor： Shaowu Huang ,  Kai Xiao ,  Beom-Taek Lee ,  Boping Wu ,  Xiaoning Ye

IPC: H01P1/24 ,  H01P1/26 ,  H01P11/00 ,  H01P3/08 ,  H01R12/73 ,  H01R13/6461 ,  H05K1/02 ,  H05K1/18 ,  H05K3/22 ,  H05K3/40 ,  G06F1/16 ,  H05K1/09 ,  H01P5/16 ,  H04L25/03 ,  H05K3/30

CPC classification number: H05K1/023 ,  G06F1/16 ,  H01P1/268 ,  H01P3/08 ,  H01P5/16 ,  H01P11/003 ,  H01R12/737 ,  H01R13/6461 ,  H04L25/03006 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0246 ,  H05K1/0268 ,  H05K1/09 ,  H05K1/181 ,  H05K3/22 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/10159 ,  H05K2201/10204

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.

公开(公告)号：US20170243705A1

公开(公告)日：2017-08-24

申请号：US15436708

申请日：2017-02-17

Applicant: Samsung Electronics Co., Ltd

Inventor： Myung-Hyo Bae ,  Young-Tae Kim ,  Sang-Hun Park ,  Jin-Wan An

IPC: H01H13/14 ,  G07C9/00 ,  H01H13/06 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01H13/14 ,  G07C9/00563 ,  G07C2009/00968 ,  H01H13/06 ,  H04M1/0277 ,  H04M1/18 ,  H04M1/23 ,  H04M2250/12 ,  H05K1/028 ,  H05K1/147 ,  H05K1/18 ,  H05K1/189 ,  H05K2201/10053 ,  H05K2201/10204

Abstract: Disclosed are various embodiments relating to an electronic device that includes a key An electronic device may include a housing having a through-hole formed therein. A key may be exposed through the through-hole and configured to be pressed. A key switch may be located on a rear surface of the key, wherein the key structure may be configured to enable the key to be pressed and to detect the press of the key. Moreover, a structure provided on a lower portion of the housing may be able to bear a pressure exerted by a user when pressing the key in a direction opposite the housing. Further, a dummy detachably provided between the housing and the structure, wherein the dummy, when being attached, may support the key and the key switch such that both are capable of being pressed in the through-hole toward the direction of the structure.