公开(公告)号：US20110271523A1

公开(公告)日：2011-11-10

申请号：US13184977

申请日：2011-07-18

Applicant: Frank Mantz

Inventor： Frank Mantz

IPC: H05K3/36

CPC classification number: H05K1/144 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/181 ,  H05K2201/042 ,  H05K2201/10378 ,  Y10T29/49126 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The invention discloses a device comprising a stack of at least two layers, which may comprise active or passive discrete components, TSOP and/or ball grid array packages, flip chip or wire bonded bare die or the like, which layers are stacked and . interconnected to define an integral module. A first and second layer comprise an electrically conductive trace with one or more electronic components in electrical connection therewith. The electrically conductive traces terminate at a lateral surface of each of the layers to define an access lead. An interposer structure is disposed between the layers and provides an interposer lateral surface upon which a conductive layer interconnect trace is defined to create an electrical connection between predetermined access leads on each of the layers.

Abstract translation: 本发明公开了一种包括至少两个层的叠层的器件，其可以包括有源或无源分立元件，TSOP和/或球栅阵列封装，倒装芯片或线接合裸片等，这些层被堆叠。 互连以定义一个整体模块。 第一层和第二层包括具有与其电连接的一个或多个电子部件的导电迹线。 导电迹线终止于每个层的侧表面以限定接入引线。 中间层结构设置在层之间并提供插入器侧表面，在该表面上定义导电层互连迹线以在每个层上的预定接触引线之间形成电连接。

公开(公告)号：US20110256662A1

公开(公告)日：2011-10-20

申请号：US13167203

申请日：2011-06-23

Applicant: Takaharu YAMANO ,  Hajime IIZUKA ,  Hideaki SAKAGUCHI ,  Toshio KOBAYASHI ,  Tadashi ARAI ,  Tsuyoshi KOBAYASHI ,  Tetsuya KOYAMA ,  Kiyoaki IIDA ,  Tomoaki MASHIMA ,  Koichi TANAKA ,  Yuji KUNIMOTO ,  Takashi YANAGISAWA

Inventor： Takaharu YAMANO ,  Hajime IIZUKA ,  Hideaki SAKAGUCHI ,  Toshio KOBAYASHI ,  Tadashi ARAI ,  Tsuyoshi KOBAYASHI ,  Tetsuya KOYAMA ,  Kiyoaki IIDA ,  Tomoaki MASHIMA ,  Koichi TANAKA ,  Yuji KUNIMOTO ,  Takashi YANAGISAWA

IPC: H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/185 ,  H05K1/186 ,  H05K3/20 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/10007 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

Abstract translation: 公开了一种制造芯片嵌入式基板的方法。 该方法包括将半导体芯片安装在其上形成有第一布线的第一基板上的第一步骤; 以及将第一基板与形成有第二布线的第二基板接合的第二步骤。 在第二步骤中，将半导体芯片封装在第一基板和第二基板之间，并且在第一布线和第二布线之间形成电连接，以形成连接到半导体芯片的多层布线。

公开(公告)号：US08030752B2

公开(公告)日：2011-10-04

申请号：US12213796

申请日：2008-06-24

Applicant: Nobuyuki Ikeguchi ,  Keungjin Sohn ,  JoonSik Shin ,  Jung-Hwan Park

Inventor： Nobuyuki Ikeguchi ,  Keungjin Sohn ,  JoonSik Shin ,  Jung-Hwan Park

IPC: H01L23/04 ,  H01L23/12

CPC classification number: H05K1/144 ,  H01L23/13 ,  H01L23/145 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H05K1/0366 ,  H05K1/056 ,  H05K1/182 ,  H05K3/4608 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10674

Abstract: A method of manufacturing a semiconductor package may include: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs.

Abstract translation: 制造半导体封装的方法可以包括：形成第一板; 在其中形成有至少一个空腔的第二板; 将第二板连接到第一板的两侧，使得第二板与第一板电连接; 以及通过将所述部件嵌入所述空腔中，通过倒装芯片方法将至少一个部件与所述第一板连接。 该方法可以防止对半导体芯片的损坏并降低制造成本，同时连接材料还可以减轻应力，防止板和半导体芯片中的开裂，同时​​防止诸如弯曲和翘曲的缺陷。 也可以避免温度变化引起的缺陷。 此外，不需要在半导体芯片与印刷电路板连接的部分中使用底部填充，这允许更容易的返工和降低成本。

公开(公告)号：US08030137B2

公开(公告)日：2011-10-04

申请号：US13048112

申请日：2011-03-15

Applicant: Kurt P Wachtler

Inventor： Kurt P Wachtler

IPC: H01L21/00

CPC classification number: H01L25/0657 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H05K1/028 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K2201/041 ,  H05K2201/10378 ,  H01L2224/05599

Abstract: A semiconductor device with a first (101) and a second (111) semiconductor chip assembled on an insulating flexible interposer (120). The interposer, preferably about 25 to 50 μm thick, has conductive traces (121), a central planar rectangular area and on each side of the rectangle a wing bent at an angle from the central plane. The central area has metal studs (122, 123) on the top and the bottom surface, which match the terminals of the chips, further conductive vias of a pitch center-to-center about 50 μm or less. The side wings have contact pads (130) with metallic connectors (131) on the bottom surface; the connectors may be solder balls, metal studs, or anisotropic conductive films. The second chip is adhesively attached to a substrate, whereby the interposer faces away from the substrate. The interposer side wings have a convex bending (150) downwardly along the second chip and a concave bending (151) over the substrate; the side wing connectors are attached to the matching substrate sites.

公开(公告)号：US08024856B2

公开(公告)日：2011-09-27

申请号：US12010197

申请日：2008-01-22

Applicant: Jong-Jin Lee

Inventor： Jong-Jin Lee

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K3/423 ,  H05K1/116 ,  H05K3/025 ,  H05K3/181 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4661 ,  H05K2201/0355 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1152 ,  Y10S205/92 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: A method of manufacturing a printed circuit board is disclosed. A method of manufacturing a printed circuit board, which includes: forming at least one interlayer connector on a first carrier, stacking at least one insulation layer on the first carrier such that the interlayer connector is exposed, removing the first carrier, and forming at least one circuit pattern on the insulation layer such that the circuit pattern is electrically coupled with the interlayer connector, can be used to increase the density of circuit patterns, as the method can provide electrical connection between circuit patterns and vias without using lands.

Abstract translation: 公开了一种制造印刷电路板的方法。 一种制造印刷电路板的方法，包括：在第一载体上形成至少一个层间连接器，在第一载体上堆叠至少一个绝缘层，使得层间连接器暴露，去除第一载体，至少形成 绝缘层上的一个电路图案使得电路图案与层间连接器电耦合，可以用于增加电路图案的密度，因为该方法可以在不使用焊盘的情况下提供电路图案和通孔之间的电连接。

公开(公告)号：US08008582B2

公开(公告)日：2011-08-30

申请号：US11908517

申请日：2006-03-21

Applicant: Masashi Shimada

Inventor： Masashi Shimada

IPC: H05K1/09 ,  H05K1/11

CPC classification number: H01L23/49827 ,  H01L23/49894 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H05K3/323 ,  H05K2201/10378 ,  H05K2201/10424 ,  H01L2924/00

Abstract: An anisotropic electrically conductive structure comprising: a dielectric matrix having a first surface and a second surface; a heat curable adhesive layer disposed on at least one or both of said first surface and said second surface; a plurality of passages at least extending from said first surface of said matrix to said second surface of said matrix; and electrically conductive members in said passages; wherein said dielectric matrix does not exhibit thermal fluidization at a temperature required for heat curing of said heat curable adhesive layer.

Abstract translation: 一种各向异性导电结构，包括：具有第一表面和第二表面的介电矩阵; 设置在所述第一表面和所述第二表面中的至少一个或两个上的热固化粘合剂层; 至少从所述基体的所述第一表面延伸到所述基体的所述第二表面的多个通道; 和所述通道中的导电构件; 其中所述介质基质在所述热固化性粘合剂层的热固化所需的温度下不显示热流化。

公开(公告)号：US08007288B2

公开(公告)日：2011-08-30

申请号：US12566923

申请日：2009-09-25

Applicant: Kelley E. Yetter ,  Anand Desai ,  John Pyle ,  Jae Choi

Inventor： Kelley E. Yetter ,  Anand Desai ,  John Pyle ,  Jae Choi

IPC: H01R12/00

CPC classification number: H01R31/06 ,  G01N29/262 ,  G01R1/0416 ,  H01R12/7082 ,  H01R12/712 ,  H01R2201/20 ,  H05K1/144 ,  H05K2201/10189 ,  H05K2201/10325 ,  H05K2201/10356 ,  H05K2201/10378

Abstract: An apparatus for connecting a multi-conductor cable of a first device to a pin grid array connector of a second device, wherein said apparatus comprises a first printed circuit board (PCB) for terminating the conductors of the cable, which are connected to a first PCB surface mounted connector mounted on the first PCB. The first PCB surface mounted connector is mated with a second PCB surface mounted connector mounted on a second PCB, on which a PCB surface mounted socket grid array is also mounted for mating to the pin grid array connector of the second device. This apparatus allows the same (i.e., standardized) multi-conductor cable with the same first PCB and the same first PCB surface mounted connector to be used regardless of what style connector is used by the second device.

Abstract translation: 一种用于将第一装置的多导体电缆连接到第二装置的针阵列连接器的装置，其中所述装置包括用于端接所述电缆的导体的第一印刷电路板（PCB），所述第一印刷电路板连接到第一装置 PCB表面安装连接器安装在第一个PCB上。 第一PCB表面安装连接器与安装在第二PCB上的第二PCB表面安装连接器配合，其上还安装有PCB表面安装的插座格栅阵列，用于配合到第二设备的引脚格栅阵列连接器。 该装置允许使用具有相同的第一PCB和相同的第一PCB表面安装的连接器的相同（即标准化）多导体电缆，而不管第二装置使用什么样的连接器。

公开(公告)号：US07990727B1

公开(公告)日：2011-08-02

申请号：US11731154

申请日：2007-03-31

Applicant: Frank Mantz

Inventor： Frank Mantz

IPC: H05K1/14

CPC classification number: H05K1/144 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/181 ,  H05K2201/042 ,  H05K2201/10378 ,  Y10T29/49126 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The invention discloses a device comprising a stack of at least two layers, which may comprise active or passive discrete components, TSOP and/or ball grid array packages, flip chip or wire bonded bare die or the like, which layers are stacked and interconnected to define an integral module. A first and second layer comprise an electrically conductive trace with one or more electronic components in electrical connection therewith. The electrically conductive traces terminate at a lateral surface of each of the layers to define an access lead. An interposer structure is disposed between the layers and provides an interposer lateral surface upon which a conductive layer interconnect trace is defined to create an electrical connection between predetermined access leads on each of the layers.

Abstract translation: 本发明公开了一种包括至少两个层的堆叠的器件，其可以包括主动或无源分立组件，TSOP和/或球栅阵列封装，倒装芯片或线接合裸芯片等，这些层被堆叠并互连到 定义一个整体模块。 第一层和第二层包括具有与其电连接的一个或多个电子部件的导电迹线。 导电迹线终止于每个层的侧表面以限定接入引线。 中间层结构设置在层之间并提供插入器侧表面，在该表面上定义导电层互连迹线以在每个层上的预定接触引线之间形成电连接。

公开(公告)号：US07989929B2

公开(公告)日：2011-08-02

申请号：US11930217

申请日：2007-10-31

Applicant: Joseph C. Fjelstad ,  Para K. Segaram ,  Belgacem Haba

Inventor： Joseph C. Fjelstad ,  Para K. Segaram ,  Belgacem Haba

IPC: H01L23/48

CPC classification number: H05K1/147 ,  H01L23/49805 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0228 ,  H05K1/0237 ,  H05K3/222 ,  H05K2201/10356 ,  H05K2201/10378 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board.

Abstract translation: 一种直接连接信号系统，包括印刷电路板和布置在印刷电路板上的第一和第二集成电路封装。 多个电信号导体在悬挂在印刷电路板上的第一和第二集成电路封装之间延伸。

公开(公告)号：US20110174530A1

公开(公告)日：2011-07-21

申请号：US12884737

申请日：2010-09-17

Applicant: Qing Man Suen

Inventor： Qing Man Suen

IPC: H05K1/11

CPC classification number: H05K3/368 ,  B23K1/0016 ,  B23K3/0623 ,  H05K2201/10303 ,  H05K2201/10378 ,  H05K2203/041

Abstract: A solder ball pin substantially includes a pillar pin body and an insulator whose opposite end facing a solder ball is formed by a soldering end. On the soldering end, a solderable metal layer is disposed concentrically with the insulator. A small opening whose dimension fits to a diameter of the pin body is defined on a center of the solderable metal layer. A reball end of the pin body penetrates the small opening on the solderable metal layer for fixing to the insulator body. The shape of the pin body could be alternatively formed by a terrace or shaped like a light beam without limitation of apertures with any varied diameters, which results in a flexible structure and the enhanced productivity. The solderable metal layer on the insulator allows the insulator to be solderable; a connection between the pin body and the insulator with the solderable metal layer becomes more compact, and the reliability of the soldering is promoted. Except the soldering part of the pin body, other non-soldered part of the pin body is wrapped in the insulator, which prevents the pin body from the oxidization and an inferior quality. Moreover, the assemblage of the insulator and the pin body does not readily deviate in view of any external force even after the soldering is processed. Thus, the assemblage is precise and controllable.

Abstract translation: 焊球销基本上包括柱销主体和绝缘体，其相对端面对焊球由焊接端形成。 在焊接端，可焊接的金属层与绝缘体同心地设置。 在可焊接金属层的中心上限定尺寸适合于针体直径的小开口。 针体的弹珠端穿过可焊接金属层上的小开口，用于固定到绝缘体上。 销主体的形状可以由平台形成，或者形状如光束，而不限制具有任何不同直径的孔，这导致柔性结构和提高的生产率。 绝缘体上的可焊接金属层允许绝缘体可焊接; 可焊接金属层之间的引线体和绝缘体之间的连接变得更加紧凑，并且促进了焊接的可靠性。 除了针体的焊接部分之外，销体的其他非焊接部分被包裹在绝缘体中，防止针体氧化，质量差。 此外，即使在焊接被加工之后，绝缘体和针体的组合也不会因任何外力而偏离。 因此，组合是精确和可控的。