公开(公告)号：US20250155493A1

公开(公告)日：2025-05-15

申请号：US18389379

申请日：2023-11-14

Applicant: SMART Modular Technologies, Inc.

Inventor： Fong-Long Lin

IPC: G01R31/28 ,  G01R31/3183 ,  G01R31/319

Abstract: Systems and methods for forced early failure of cells within a memory device are disclosed. A memory device such as a dynamic random-access memory (DRAM) chip is subjected to an elevated temperature and an electric field to cause unwanted particles within the chip to migrate rapidly into the circuit elements of a memory cell, thereby causing the memory cell to fail. Subsequent testing may identify this failed cell and verify that the remaining cells within the memory device are operational. By forcing the cell to fail prior to certification testing, the end user may be reasonably confident that the certification provided for the device will remain accurate for the lifetime of the device. In contrast, without this forced early failure, such unwanted particles may migrate after deployment and may cause cell failure while deployed resulting in a botched operation.

公开(公告)号：US20240126894A1

公开(公告)日：2024-04-18

申请号：US17964663

申请日：2022-10-12

Applicant: SMART Modular Technologies, Inc.

Inventor： Victor Y. Tsai

IPC: G06F21/60 ,  G06F21/31 ,  G06F21/78

CPC classification number: G06F21/602 ,  G06F21/31 ,  G06F21/78

Abstract: Techniques for a host system or a user to verify the authenticity of a storage device or a logical sub-unit (e.g., a partition) of the storage device are disclosed. A storage device stores one or more first secret keys and a host device stores one or more second keys. A respective first secret key and a respective second key are used in a verification process that verifies the authenticity of the storage device prior to accessing the storage device.

公开(公告)号：US20180107400A1

公开(公告)日：2018-04-19

申请号：US15294678

申请日：2016-10-14

Applicant: SMART Modular Technologies, Inc.

Inventor： Victor Y. Tsai ,  Robert Fillion

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/7201

Abstract: Approaches, techniques, and mechanisms are disclosed for a method of operation of a Flash-based block storage system including: transferring a first data to a logical block address; storing the first data in a physical block, of a storage array, associated with the logical block address; receiving a trim command for the logical block address; establishing a reserved physical block associated with the logical block address of the trim command; transferring second data for writing to the logical block address of the trim command; releasing the reserved physical block associated with the logical block address; and writing the second data to the logical block address.

公开(公告)号：US20180081554A1

公开(公告)日：2018-03-22

申请号：US15273385

申请日：2016-09-22

Applicant: SMART Modular Technologies, Inc.

Inventor： Satyanarayan Shivkumar Iyer ,  Robert S. Pauley, JR.

IPC: G06F3/06

Abstract: Approaches, techniques, and mechanisms are disclosed for manufacturing and operating high density memory systems. The high density memory systems can increase the amount of memory available to a computing system by allowing the connection of multiple memory modules into a single memory interface on a motherboard via a memory adapter as described herein.

公开(公告)号：US20170315949A1

公开(公告)日：2017-11-02

申请号：US15141757

申请日：2016-04-28

Applicant: SMART Modular Technologies, Inc.

Inventor： Rajesh Ananthanarayanan

IPC: G06F13/40 ,  G06F3/06

CPC classification number: G06F13/4068

Abstract: An interconnected memory system, and a method of operation thereof, including: a first discrete unit having a first unit processor and first unit memory module; a high-speed interconnect connected directly to the first unit memory module; and a second discrete unit having a second unit processor and a second unit memory module, the second unit memory module connected to the first unit memory module through the high-speed interconnect for utilizing the first unit memory module and the second unit memory module with the first unit processor.

公开(公告)号：US20160105510A1

公开(公告)日：2016-04-14

申请号：US14512624

申请日：2014-10-13

Applicant: SMART Modular Technologies, Inc.

Inventor： Fong-Long Lin ,  Michael Rubino

IPC: H04L29/08

Abstract: A data storage system, and a method of operation thereof, includes: a host initialization module for initializing a data storage unit; a command process module, coupled to the host initialization module, for processing a read command or a write command performed on the data storage unit; and a status scheduler module, coupled to the command process module, for generating a check status request to inquire a storage unit status of the data storage unit, wherein the check status request occurs without interrupting a host.

Abstract translation: 数据存储系统及其操作方法包括：主机初始化模块，用于初始化数据存储单元; 命令处理模块，耦合到所述主机初始化模块，用于处理对所述数据存储单元执行的读取命令或写入命令; 以及状态调度器模块，其耦合到所述命令处理模块，用于生成查询数据存储单元的存储单元状态的检查状态请求，其中所述检查状态请求发生而不中断主机。

公开(公告)号：US20250077089A1

公开(公告)日：2025-03-06

申请号：US18239376

申请日：2023-08-29

Applicant: SMART Modular Technologies, Inc.

Inventor： Andrew Mills ,  Torry Steed

IPC: G06F3/06

Abstract: Systems and methods for memory snapshots are disclosed. In particular, a memory device may include a volatile section and a backup persistent storage section. A snapshot manager circuit is positioned between a host control circuit or central processors. This snapshot manager circuit acts as a memory virtualization layer within the memory device and may use a redirect on write type command to put a snapshot of actively changed memory to a reserved memory area in the volatile section. A background function may copy the snapshots to the persistent storage section. Because the snapshot manager circuit is in the hardware memory access layers of the memory device, operation of the application is not interrupted or paused to access the specific memory sections. Further, snapshots are more readily available in the memory used by the host control circuit.

公开(公告)号：US11561739B1

公开(公告)日：2023-01-24

申请号：US16889729

申请日：2020-06-01

Applicant: SMART Modular Technologies, Inc.

Inventor： Kelvin Alberto Marino

IPC: G06F3/06 ,  G06F1/30 ,  G06F11/14

Abstract: A persistent memory unit for a computer system where the memory unit can detect a catastrophic event and automatically backup volatile memory into non-volatile memory. The memory unit can operate with a limited number of power inputs and detect the loss of power and then initiate a backup after the volatile memory of the memory unit has entered a stable self-refresh mode. The memory unit uses an on-board power management interface controller capable of redistributing power from an input power line and generating different power levels for different components on the memory unit.

公开(公告)号：US10573354B2

公开(公告)日：2020-02-25

申请号：US15273385

申请日：2016-09-22

Applicant: SMART Modular Technologies, Inc.

Inventor： Satyanarayan Shivkumar Iyer ,  Robert S. Pauley, Jr.

IPC: G06F12/00 ,  G11C7/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06

Abstract: Approaches, techniques, and mechanisms are disclosed for manufacturing and operating high density memory systems. The high density memory systems can increase the amount of memory available to a computing system by allowing the connection of multiple memory modules into a single memory interface on a motherboard via a memory adapter as described herein.

公开(公告)号：US20180095661A1

公开(公告)日：2018-04-05

申请号：US15285305

申请日：2016-10-04

Applicant: SMART Modular Technologies, Inc.

Inventor： Rajesh Ananthanarayanan ,  Jinying Shen ,  Amir Alavi

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673

Abstract: Approaches, techniques, and mechanisms are disclosed for improving the performance of memory controllers for memory devices. A system may have a memory controller that interfaces with a memory device to store or retrieve information. When the system needs to retrieve information from the memory device, the memory controller sends an address and a command to instruct the memory device to read the information stored at the address. The memory device reads the information, and after a specific amount of time, the memory device sends the information to the memory controller. According to an embodiment, “dummy” data is sent first prior to the availability of the data read out of the memory devices, while waiting for the requested data to be accessed, and then the actual data is sent immediately following the dummy data. According to an embodiment, a geometry of a memory device has only one column of memory cells that are used to store information. The memory device with only one column in an embodiment does not require decoding of a column address. As such, the read latency of the memory device is significantly reduced.