公开(公告)号：US20160042917A1

公开(公告)日：2016-02-11

申请号：US14923077

申请日：2015-10-26

Applicant: APPLIED MATERIALS, INC.

Inventor： Madhavi R. Chandrachood ,  Michael N. Grimbergen ,  Khiem K. Nguyen ,  Richard Lewington ,  Ibrahim M. Ibrahim ,  Sheeba J. Panayil ,  Ajay Kumar

IPC: H01J37/32

CPC classification number: H01J37/3211 ,  C23C16/45561 ,  C23C16/45563 ,  C23C16/4586 ,  C23C16/52 ,  H01J37/32449 ,  H01J37/32715 ,  H01J37/32935 ,  H01J37/32963 ,  H01J2237/334 ,  H01L21/67253 ,  H01L21/68785

Abstract: A plasma reactor has an array of plural gas injectors arranged around a circular side wall that are individually controlled.

Abstract translation: 等离子体反应器具有围绕圆形侧壁布置的多个气体喷射器的阵列，其被单独控制。

公开(公告)号：US09245803B1

公开(公告)日：2016-01-26

申请号：US14517287

申请日：2014-10-17

Applicant: Applied Materials, Inc.

Inventor： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/78 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/67 ,  H01J37/32 ,  B23K26/36 ,  B23K26/16

CPC classification number: H01L21/78 ,  B23K26/16 ,  H01L21/02057 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/32131 ,  H01L21/67092 ,  H01L21/67207

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a Bessel beam shaper laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个例子中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模由覆盖并保护集成电路的层组成。 然后用贝塞尔光束成形器激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。 然后通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US09224625B2

公开(公告)日：2015-12-29

申请号：US13943652

申请日：2013-07-16

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Madhava Rao Yalamanchili ,  Brad Eaton ,  Saravjeet Singh ,  Ajay Kumar

IPC: H01L21/00 ,  H01L21/67 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/683 ,  B23K26/06 ,  B23K26/36 ,  B23K26/40

CPC classification number: H01L21/67069 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a water-soluble die attach film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模。 半导体晶片设置在水溶性芯片附着膜上。 面罩覆盖并保护集成电路。 用激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模。 图案化使得集成电路之间的半导体晶片的区域露出。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以形成单独的集成电路。 然后用水溶液对水溶性贴片膜进行构图。

公开(公告)号：US09177824B2

公开(公告)日：2015-11-03

申请号：US14301847

申请日：2014-06-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Banqiu Wu ,  Ajay Kumar ,  Leonid Dorf ,  Shahid Rauf ,  Kartik Ramaswamy ,  Omkaram Nalamasu

IPC: H01L21/311 ,  H01L21/027 ,  G03F7/004 ,  G03F7/00 ,  H01J37/32

CPC classification number: H01L21/31138 ,  G03F7/00 ,  G03F7/0035 ,  G03F7/004 ,  H01J37/32091 ,  H01J37/3233 ,  H01J37/3266 ,  H01L21/0273

Abstract: Methods for reducing the line width roughness on a photoresist pattern are provided herein. In some embodiments, a method of processing a patterned photoresist layer disposed atop a substrate includes flowing a process gas into a processing volume of a process chamber having the substrate disposed therein; forming a plasma within the process chamber from the process gas, wherein the plasma has a ion energy of about 1 eV to about 10 eV; and etching the patterned photoresist layer with species from the plasma to at least one of smooth a line width roughness of a sidewall of the patterned photoresist layer or remove debris.

Abstract translation: 本文提供了减少光致抗蚀剂图案上的线宽粗糙度的方法。 在一些实施例中，处理设置在基板顶上的图案化光致抗蚀剂层的方法包括将工艺气体流入其中布置有衬底的处理室的处理容积; 在所述处理室内从所述处理气体形成等离子体，其中所述等离子体具有约1eV至约10eV的离子能; 以及将来自等离子体的物质的图案化光致抗蚀剂层蚀刻成图案化光致抗蚀剂层的侧壁的线宽粗糙度的至少一个或去除碎屑。

公开(公告)号：US09105710B2

公开(公告)日：2015-08-11

申请号：US14091014

申请日：2013-11-26

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Aparna Iyer ,  Madhava Rao Yalamanchili ,  Ajay Kumar ,  Jungrae Park

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67 ,  B23K26/36

CPC classification number: H01L21/78 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/67069 ,  H01L21/67207

Abstract: In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation while also removing an oxidation layer from metal bumps on the wafer. In one embodiment, a method includes forming a mask over the semiconductor wafer covering the plurality of ICs, the plurality of ICs including metal bumps or pads with an oxidation layer. The method includes patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the ICs. The method includes plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of ICs and remove the oxidation layer from the metal bumps or pads.

Abstract translation: 在实施例中，涉及初始激光划片和随后等离子体蚀刻的混合晶片或衬底切割工艺被实现用于裸片分离，同时还从晶片上的金属凸块去除氧化层。 在一个实施例中，一种方法包括在覆盖多个IC的半导体晶片上形成掩模，所述多个IC包括具有氧化层的金属凸块或焊盘。 该方法包括用激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模，暴露半导体晶片在IC之间的区域。 该方法包括通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以分离多个IC并从金属凸块或焊盘移除氧化层。

公开(公告)号：US20230207393A1

公开(公告)日：2023-06-29

申请号：US18116736

申请日：2023-03-02

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065

CPC classification number: H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67207 ,  H01L23/544 ,  H01L21/6836 ,  H01L21/67092 ,  H01L2924/0002

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US11355394B2

公开(公告)日：2022-06-07

申请号：US16516926

申请日：2019-07-19

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/3213 ,  H01L21/82

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to patterning the mask, a breakthrough treatment is performed, the breakthrough treatment comprising a first physical bombardment operation, a second iterative isotropic and directional plasma etch operation, and a third directional breakthrough operation. Subsequent to performing the breakthrough treatment, the semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US11217536B2

公开(公告)日：2022-01-04

申请号：US15945966

申请日：2018-04-05

Applicant: APPLIED MATERIALS, INC.

Inventor： Jungrae Park ,  Wei-Sheng Lei ,  Brad Eaton ,  James S. Papanu ,  Ajay Kumar

IPC: H01L23/544 ,  A47G19/22 ,  B65D47/24 ,  B65D47/32 ,  B23K26/0622 ,  B23K10/00 ,  H01L21/78

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a split laser beam laser scribing process, such as a split shaped laser beam laser scribing process, to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US10535561B2

公开(公告)日：2020-01-14

申请号：US15918673

申请日：2018-03-12

Applicant: APPLIED MATERIALS, INC.

Inventor： Jungrae Park ,  James S. Papanu ,  Ajay Kumar ,  Wei-Sheng Lei

IPC: H01L21/78 ,  H01L21/263 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/308 ,  B23K10/00 ,  B23K26/53 ,  H01L21/67 ,  H01L21/311 ,  B23K101/40

Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer having integrated circuits thereon involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a multiple pass laser scribing process to provide a patterned mask with gaps exposing regions of the semiconductor wafer between the integrated circuits, the multiple pass laser scribing process including a first pass along a first edge scribing path, a second pass along a center scribing path, a third pass along a second edge scribing path, a fourth pass along the second edge scribing path, a fifth pass along the center scribing path, and a sixth pass along the first edge scribing path. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US09312177B2

公开(公告)日：2016-04-12

申请号：US14099707

申请日：2013-12-06

Applicant: Applied Materials, Inc.

Inventor： Prabhat Kumar ,  Brad Eaton ,  Wei-Sheng Lei ,  James S. Papanu ,  Ajay Kumar

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/3065 ,  B41F15/08 ,  H01L21/67 ,  H01J37/32

CPC classification number: H01L21/78 ,  B23K26/364 ,  B41F15/08 ,  H01J37/32091 ,  H01J37/321 ,  H01J2237/334 ,  H01L21/3043 ,  H01L21/3065 ,  H01L21/67207

Abstract: Methods of using a screen-print mask for hybrid wafer dicing using laser scribing and plasma etch described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits separated by streets involves screen-printing a patterned mask above the semiconductor wafer, the patterned mask covering the integrated circuits and exposing the streets of the semiconductor wafer. The method also involves laser ablating the streets with a laser scribing process to expose regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the exposed regions of the semiconductor wafer to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching.

Abstract translation: 使用激光划线和等离子体蚀刻使用用于混合晶片切割的丝网印刷掩模的方法。 在一个示例中，对具有由街道分开的多个集成电路进行切割的半导体晶片的方法涉及在半导体晶片之上丝网印刷图案化掩模，该图案化掩模覆盖集成电路并暴露半导体晶片的街道。 该方法还涉及通过激光划线工艺激光烧蚀街道，以暴露集成电路之间的半导体晶片的区域。 该方法还包括通过半导体晶片的暴露区域等离子体蚀刻半导体晶片以对集成电路进行分离。 图案化掩模在等离子体蚀刻期间保护集成电路。