公开(公告)号：US20230253248A1

公开(公告)日：2023-08-10

申请号：US18119080

申请日：2023-03-08

Applicant: Applied Materials, Inc.

Inventor： Yang Zhou ,  Yong Jin Kim ,  Ge Qu ,  Zhiyuan Wu ,  Carmen Leal Cervantes ,  Feng Chen ,  Kevin Kashefi ,  Bhaskar Jyoti Bhuyan ,  Drew Phillips ,  Aaron Dangerfield

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L23/5226 ,  H01L21/28568

Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM comprises a hydrocarbon having a formula of H—C≡C—R, wherein R is a linear alkyl chain or aryl group comprising from 1 to 20 carbon atoms or a formula of R′C═CR″, wherein R′ and R″ independently include a linear alkyl chain or aryl group comprising from 1 to 20 carbon atoms A barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

公开(公告)号：US20220344275A1

公开(公告)日：2022-10-27

申请号：US17858274

申请日：2022-07-06

Applicant: Applied Materials, Inc.

Inventor： Wenjing Xu ,  Feng Chen ,  Tae Hong Ha ,  Xianmin Tang ,  Lu Chen ,  Zhiyuan Wu

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.

公开(公告)号：US20220028795A1

公开(公告)日：2022-01-27

申请号：US17383361

申请日：2021-07-22

Applicant: Applied Materials, Inc.

Inventor： Wenjing Xu ,  Feng Chen ,  Tae Hong Ha ,  Xianmin Tang ,  Lu Chen ,  Zhiyuan Wu

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.

公开(公告)号：US10410918B2

公开(公告)日：2019-09-10

申请号：US15874041

申请日：2018-01-18

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan Wu ,  Nikolaos Bekiaris ,  Mehul B. Naik ,  Jin Hee Park ,  Mark Hyun Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/288 ,  H01L21/285 ,  H01L21/67

Abstract: In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition.

公开(公告)号：US20170309515A1

公开(公告)日：2017-10-26

申请号：US15137245

申请日：2016-04-25

Applicant: APPLIED MATERIALS, INC.

Inventor： He Ren ,  Jie Zhou ,  Guannan Chen ,  Michael W. Stowell ,  Bencherki Mebarki ,  Mehul Naik ,  Srinivas D. Nemani ,  Nikolaos Bekiaris ,  Zhiyuan Wu

IPC: H01L21/768

CPC classification number: H01L21/76883 ,  H01L21/28556 ,  H01L21/76877 ,  H01L23/53209

Abstract: An integrated circuit is fabricated by chemical vapor deposition or atomic layer deposition of a metal film to metal film.

公开(公告)号：US09570345B1

公开(公告)日：2017-02-14

申请号：US15075039

申请日：2016-03-18

Applicant: APPLIED MATERIALS, INC.

Inventor： Nikolaos Bekiaris ,  Mehul Naik ,  Zhiyuan Wu

IPC: H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/02074 ,  H01L21/76814 ,  H01L21/76832 ,  H01L21/76883 ,  H01L23/53209

Abstract: Resistance increase in Cobalt interconnects due to nitridation occurring during removal of surface oxide from Cobalt interconnects and deposition of Nitrogen-containing film on Cobalt interconnects is solved by a Hydrogen thermal anneal or plasma treatment. Removal of the Nitrogen is through a thin overlying layer which may be a dielectric barrier layer or an etch stop layer.

Abstract translation: 通过氢热退火或等离子体处理，可以解决由于从Cobalt互连中去除表面氧化物时发生的氮化而导致的钴互连的电阻增加和含钴膜在钴互连上的沉积。 通过可以是介电阻挡层或蚀刻停止层的薄的上覆层去除氮。

公开(公告)号：US20240339358A1

公开(公告)日：2024-10-10

申请号：US18131956

申请日：2023-04-07

Applicant: Applied Materials, Inc.

Inventor： Jesus Candelario Mendoza-Gutierrez ,  Aaron Dangerfield ,  Bhaskar Jyoti Bhuyan ,  Mark Saly ,  Yang Zhou ,  Yong Jin Kim ,  Carmen Leal Cervantes ,  Ge Qu ,  Zhiyuan Wu ,  Feng Chen ,  Kevin Kashefi

IPC: H01L21/768 ,  C23C16/18 ,  C23C16/455 ,  C23C16/56

CPC classification number: H01L21/76846 ,  C23C16/18 ,  C23C16/45527 ,  C23C16/56 ,  H01L21/76877

Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM has a general formula I to XIX, wherein R, R′, R1, R2, R3, R4, and R5 are independently selected from hydrogen (H), alkyl, alkene, alkyne, and aryl, n is from 1 to 20, m is from 1 to 20, x is from 1 to 2, and y is from 1 to 2. A barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

公开(公告)号：US11587873B2

公开(公告)日：2023-02-21

申请号：US16909148

申请日：2020-06-23

Applicant: Applied Materials, Inc.

Inventor： Gang Shen ,  Feng Chen ,  Yizhak Sabba ,  Tae Hong Ha ,  Xianmin Tang ,  Zhiyuan Wu ,  Wenjing Xu

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Described are microelectronic devices comprising a dielectric layer formed on a substrate, a feature comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming a microelectronic device comprising the two metal liner film on the barrier layer.

公开(公告)号：US11373903B2

公开(公告)日：2022-06-28

申请号：US15722639

申请日：2017-10-02

Applicant: Applied Materials, Inc.

Inventor： Mehul B. Naik ,  Zhiyuan Wu

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/285

Abstract: Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes providing a substrate comprising a metal region and a dielectric region surrounding the metal region, selectively forming a cobalt-containing alloy cap layer on the metal region by exposing the substrate to a first precursor and a second precursor, the first precursor and the second precursor are selected from a group consisting of an aluminum-containing precursor, a cobalt-containing precursor, a ruthenium-containing precursor, a manganese-containing precursor, and a tungsten-containing precursor, wherein the first precursor is different from the second precursor.

公开(公告)号：US10256144B2

公开(公告)日：2019-04-09

申请号：US15498024

申请日：2017-04-26

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Feiyue Ma ,  Yu Lei ,  Kai Wu ,  Mehul B. Naik ,  Zhiyuan Wu ,  Vikash Banthia ,  Hua Al

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L23/522

Abstract: Embodiments of the present disclosure generally relate an interconnect formed on a substrate and a method of forming the interconnect thereon. In an embodiment, a via and trench in a stack formed on the substrate. A bottom of the via is pre-treated using a first pre-treatment procedure. A sidewall of the via is pre-treated using a second pre-treatment procedure. A first metal fill material of a first type is deposited on the stack, in the via. A second metal fill material of a second type is deposited on the stack, in the trench.