公开(公告)号：US20100319973A1

公开(公告)日：2010-12-23

申请号：US12851803

申请日：2010-08-06

Applicant: Chih-Peng Fan

Inventor： Chih-Peng Fan

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a first core circuit board, at least one embedded capacitor, a second core circuit board and a dielectric layer. The first core circuit board has at least one metal layer, and the first core circuit board has at least one first conductive through hole connected to the metal layer. At least one embedded capacitor is embedded in the first core circuit board and connected to the metal layer. The second core circuit board has at least one wiring layer, and the second core circuit board has at least one second conductive through hole connected to the wiring layer. The dielectric layer is laminated between the first core circuit board and the second core circuit board.

Abstract translation: 提供具有嵌入式电容器的封装基板。 封装衬底包括第一核心电路板，至少一个嵌入式电容器，第二核心电路板和电介质层。 第一核心电路板具有至少一个金属层，并且第一核心电路板具有连接到金属层的至少一个第一导电通孔。 至少一个嵌入式电容器被嵌入在第一核心电路板中并连接到金属层。 第二核心电路板具有至少一个布线层，并且第二核心电路板具有连接到布线层的至少一个第二导电通孔。 电介质层层压在第一芯电路板和第二芯电路板之间。

公开(公告)号：US20090288858A1

公开(公告)日：2009-11-26

申请号：US12181556

申请日：2008-07-29

Applicant: Chih-Peng Fan ,  Yen-Ti Chia

Inventor： Chih-Peng Fan ,  Yen-Ti Chia

IPC: H05K3/02 ,  H05K1/00

CPC classification number: H05K1/111 ,  H01L2224/16225 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/0574 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A manufacturing method of a circuit structure is provided as follows. Firstly, a base conductive layer is formed on the carrier board and a first patterned plating-resistant layer having at least one trench for exposing a part of the base conductive layer is formed on the base conductive layer. A first patterned conductive layer is then formed in the trench and a second patterned plating-resistant layer is formed which covers a part of the first patterned conductive layer and a part of the first patterned plating-resistant layer. A second patterned conductive layer is formed on the exposed first patterned conductive layer. The first and the second patterned plating-resistant layers and the base conductive layer exposed by the first patterned conductive layer are removed. Then, a patterned solder mask is formed for covering a part of the first patterned conductive layer.

Abstract translation: 电路结构的制造方法如下所述。 首先，在载体板上形成基底导电层，在基底导电层上形成具有至少一个露出基底导电层的一部分的沟槽的第一图案化电镀层。 然后在沟槽中形成第一图案化导电层，并且形成覆盖第一图案化导电层的一部分和第一图案化电镀层的一部分的第二图案化电镀层。 在暴露的第一图案化导电层上形成第二图案化导电层。 去除第一和第二图案化电镀层和由第一图案化导电层暴露的基底导电层。 然后，形成图案化的焊料掩模以覆盖第一图案化导电层的一部分。

公开(公告)号：US06709897B2

公开(公告)日：2004-03-23

申请号：US10050074

申请日：2002-01-15

Applicant: Jao-Chin Cheng ,  Chih-Peng Fan ,  David C. H. Cheng

Inventor： Jao-Chin Cheng ,  Chih-Peng Fan ,  David C. H. Cheng

IPC: H01L2144

CPC classification number: H01L23/49822 ,  H01L23/13 ,  H01L23/142 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/12105 ,  H01L2224/24246 ,  H01L2224/24247 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/24227 ,  H01L2924/00

Abstract: A method of forming an integrated circuit package with an upward-facing chip cavity such that the fabrication of the substrate and the packaging of silicon chip are combined. By forming a patterned dielectric layer to expose bonding pads on a silicon chip and subsequently connecting the bonding pad on the chip with trace lines on the substrate through electroplating, reliable connections between the chip and substrate are formed and no more bubbles are formed inside the dielectric layer.

Abstract translation: 一种形成具有朝上的芯片空腔的集成电路封装的方法，使得基板的制造和硅芯片的封装被组合。 通过形成图案化的电介质层以暴露硅芯片上的焊盘，随后通过电镀将衬底上的接合焊盘与衬底上的迹线连接，形成芯片和衬底之间的可靠连接，并且在电介质内不再形成气泡 层。

公开(公告)号：US07700986B2

公开(公告)日：2010-04-20

申请号：US12208843

申请日：2008-09-11

Applicant: Han-Pei Huang ,  Chih-Peng Fan

Inventor： Han-Pei Huang ,  Chih-Peng Fan

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/00 ,  H01L23/34 ,  H01L21/02 ,  H01L21/20 ,  H01L21/8242

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/115 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09518 ,  H05K2201/09809 ,  H01L2224/0401

Abstract: A chip package carrier is disclosed, which includes a first circuit layer, a second circuit layer, a core layer, a third circuit layer, a first dielectric layer between the first and third circuit layers, a fourth conductive layer including at least a solder ball pad, a second dielectric layer between the second and fourth circuit layers and at least a capacitor device, wherein the core layer has at least a first through-hole; the third circuit layer is disposed above the first circuit layer and includes at least a die pad; the capacitor device is disposed in the first through-hole. The capacitor device herein includes a first pillar electrode covering the wall of the first through-hole, a cylindrical capacitor material disposed in the first pillar electrode and having a first blind hole, and a second pillar electrode disposed in the first blind hole and connected to the die pad.

Abstract translation: 公开了一种芯片封装载体，其包括第一电路层，第二电路层，芯层，第三电路层，第一和第三电路层之间的第一电介质层，第四导电层，至少包括焊球 垫，第二和第四电路层之间的第二电介质层和至少一个电容器器件，其中芯层至少具有第一通孔; 所述第三电路层设置在所述第一电路层上方，并且至少包括管芯焊盘; 电容器装置设置在第一通孔中。 本发明的电容器件包括覆盖第一通孔的壁的第一柱状电极，设置在第一柱状电极中并具有第一盲孔的圆筒形电容器材料和设置在第一盲孔中的第二柱状电极， 芯片垫。

公开(公告)号：US20100044083A1

公开(公告)日：2010-02-25

申请号：US12320798

申请日：2009-02-05

Applicant: Chih-Peng Fan

Inventor： Chih-Peng Fan

IPC: H05K1/09 ,  H05K3/10

CPC classification number: H05K3/4682 ,  H05K1/115 ,  H05K3/20 ,  H05K3/205 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2203/0376 ,  Y10T29/49155

Abstract: A method of manufacturing a build-up printed circuit board structure for increasing fine circuit density includes providing a core carrier board; forming a plurality of first conductive pads on a top surface of the core carrier board; forming a first dielectric layer on the core carrier board in order to cover the first conductive pads; drilling the first dielectric layer to form a patterned first electroplated layer on the first dielectric layer; forming a second dielectric layer, and the first dielectric layer and the patterned first electroplated layer being covered by the second dielectric layer; drilling the second dielectric layer and the first dielectric layer to form a patterned second electroplated layer on the second dielectric layer; and forming a third dielectric layer, and the second dielectric layer and the patterned second electroplated layer being covered by the third dielectric layer; and removing the core carrier board.

Abstract translation: 一种制造用于增加精细电路密度的积聚印刷电路板结构的方法包括：提供芯片载体板; 在所述芯承载板的顶表面上形成多个第一导电焊盘; 在所述芯载板上形成第一电介质层以覆盖所述第一导电焊盘; 钻第一介电层以在第一电介质层上形成图案化的第一电镀层; 形成第二电介质层，并且所述第一电介质层和所述图案化的第一电镀层被所述第二电介质层覆盖; 钻第二介电层和第一介电层以在第二介电层上形成图案化的第二电镀层; 以及形成第三电介质层，并且所述第二电介质层和所述图案化的第二电镀层被所述第三电介质层覆盖; 并移除核心载板。

公开(公告)号：US06696886B1

公开(公告)日：2004-02-24

申请号：US10369080

申请日：2003-02-13

Applicant: Chun-Nan Ke ,  Cheng-Yi Huang ,  Chih-Peng Fan

Inventor： Chun-Nan Ke ,  Cheng-Yi Huang ,  Chih-Peng Fan

IPC: H03K500

CPC classification number: H04L27/38 ,  H03L7/107 ,  H03L2207/50 ,  H04L2027/0081

Abstract: An automatically adjusting gain/bandwidth loop filter suitable for a digital phase lock loop or a digital adaptive carrier recovery loop with variable loop gain/bandwidth for rapid acquisition and lower steady-state jitter is provided. The automatically adjusting gain/bandwidth loop filter comprises a variable gain/bandwidth loop filter, a tracking status detector and a gain/bandwidth control state machine. The tracking status detector observes the frequency error which is the output of the frequency tracking (integral) branch of the variable gain/bandwidth loop filter, then it outputs a tracking state of the carrier recovery loop. The loop gain/bandwidth is then adjusted by the gain/bandwidth control state machine in response of the tracking state to improve the pull-in time and steady-state carrier frequency jitter.

Abstract translation: 提供了适用于数字锁相环的自动调整增益/带宽环路滤波器或具有可变环路增益/带宽的数字自适应载波恢复环路，用于快速采集和降低稳态抖动。 自动调整增益/带宽环路滤波器包括可变增益/带宽环路滤波器，跟踪状态检测器和增益/带宽控制状态机。 跟踪状态检测器观察到可变增益/带宽环路滤波器的频率跟踪（积分）分支输出的频率误差，然后输出载波恢复循环的跟踪状态。 响应于跟踪状态，通过增益/带宽控制状态机调整环路增益/带宽，以改善引入时间和稳态载波频率抖动。

公开(公告)号：US06506632B1

公开(公告)日：2003-01-14

申请号：US10078211

申请日：2002-02-15

Applicant: Jao-Chin Cheng ,  Chih-Peng Fan ,  David C. H. Cheng

Inventor： Jao-Chin Cheng ,  Chih-Peng Fan ,  David C. H. Cheng

IPC: H01L2144

CPC classification number: H01L24/82 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method of forming an integrated circuit package with a downward-facing chip cavity. A substrate comprising an insulating core layer and a conductive layer is provided. A through-hole is formed in the substrate and an adhesive tape is attached to the surface of the conductive layer. A silicon chip is attached to the exposed adhesive tape surface at the bottom of the first opening. The chip has an active surface and a back surface. The chip further includes a plurality of bonding pads on the active surface. The back surface of the chip is attached to the adhesive tape. A patterned dielectric layer is formed filling the first opening and covering a portion of the adhesive tape, the active surface, the bonding pad and the insulating core layer. The patterned dielectric layer has a plurality of openings that exposes the bonding pads and some through holes. A metallic layer is formed over the exposed surface of the openings and the upper surface of the patterned dielectric layer by electroplating. The adhesive tape is removed. The metallic layer and the conductive layer are patterned. A patterned solder resistant layer is formed over the metallic layer and the conductive layer. The patterned solder resistant layer has a plurality of openings that expose a portion of the conductive layer. A solder ball implant is conducted to form electrical connection between the solder balls and the conductive layer.

Abstract translation: 一种形成具有朝下的芯片腔的集成电路封装的方法。 提供了包括绝缘芯层和导电层的衬底。 在基板中形成通孔，并且在导电层的表面上附着粘合带。 硅芯片附着在第一开口底部的暴露的胶带表面上。 芯片具有活性表面和背面。 所述芯片还包括在所述有源表面上的多个接合焊盘。 芯片的背面附着在胶带上。 形成图案化的介电层，填充第一开口并覆盖粘合带，活性表面，接合焊盘和绝缘芯层的一部分。 图案化电介质层具有暴露接合焊盘和一些通孔的多个开口。 通过电镀在开口的暴露表面和图案化电介质层的上表面上形成金属层。 去除胶带。 金属层和导电层被图案化。 在金属层和导电层之上形成图案化的阻焊层。 图案化的阻焊层具有暴露导电层的一部分的多个开口。 导电焊球植入物以形成焊球和导电层之间的电连接。

公开(公告)号：US20170194721A1

公开(公告)日：2017-07-06

申请号：US15401027

申请日：2017-01-07

Applicant: Chih-Peng Fan ,  Ching-Ho Hsieh ,  Min-Hsing Wu ,  David L. Chen ,  Woody James Maynard

Inventor： Chih-Peng Fan ,  Ching-Ho Hsieh ,  Min-Hsing Wu ,  David L. Chen ,  Woody James Maynard

IPC: H01R4/04 ,  H05K3/32 ,  H01R13/24 ,  H01R12/52 ,  H01R12/57

CPC classification number: H01R4/04 ,  H01R12/52 ,  H01R12/57 ,  H01R12/73 ,  H01R12/79 ,  H01R13/2442 ,  H05K1/147 ,  H05K1/189 ,  H05K3/326 ,  H05K2201/0311

Abstract: A novel electrical connector and method of manufacture is disclosed which provides an integral attachment and retention means for the purpose of electrically and mechanically interconnecting circuit elements in electronic devices, said circuit elements including but not limited to printed circuit boards, flexible printed circuits, rigid flex circuits, semiconductor package substrates, modules, and batteries. The electrical connector of the present invention utilizes a bonding material, disposed at least between the electrical spring contact elements on a surface of the connector, to bond and retain first and second portions of the electrical connector in an actuated state on a mating circuit element whereby stable and low resistance electrical interconnections are formed and maintained between the electrical connector and interconnection terminals on the mating circuit element. This design permits the electrical connector to be low-profile and use a reduced amount of space on a circuit member such as a PCB.

公开(公告)号：US20160380372A1

公开(公告)日：2016-12-29

申请号：US15192015

申请日：2016-06-24

Applicant: Ching-Ho Hsieh ,  Bohdan P. Wozniak ,  David L. Chen ,  Chih-Peng Fan ,  Ming-Hsing Wu

Inventor： Ching-Ho Hsieh ,  Bohdan P. Wozniak ,  David L. Chen ,  Chih-Peng Fan ,  Ming-Hsing Wu

IPC: H01R12/75 ,  H01R24/60 ,  H01R13/26 ,  H01R13/11 ,  H01R43/20

CPC classification number: H01R13/2442 ,  H01R12/52 ,  H01R13/03 ,  H01R24/60 ,  H01R43/16

Abstract: A novel interconnection structure and method of manufacture is provided which provides an improved means of interconnecting external connector interfaces, such as Universal Serial Bus (USB) connectors, to the internal system boards of electronic devices, such as laptop computers, tablets, and mobile phones. An external connector interface used for interconnecting separate electronic devices is connected to the internal system board of the device in which it resides by being interconnected mechanically and electrically, or alternatively being integral to and of a unitary structure with, a printed circuit substrate, said printed circuit substrate having a plurality of conductive, elastic spring contacts mounted on one surface, with at least one of said electrical spring contacts electrically interconnected to the external electrical connections of the USB connector, and said electrical spring contacts providing an electrical interconnection means to a system board inside the electronic device.This structure improves upon the state of the art by reducing the number and complexity of interconnection interfaces, reducing signal degradation, allowing higher data transfer rates, and improving reliability of the interconnections.The interconnection of the USB substrate to the system board may be separable, re-mountable, and re-connectable, and may be accomplished with a normal-force actuated connector.

Abstract translation: USB基板与系统板的互连可以是可分离的，可重新安装的和可重新连接的，并且可以用法向力致动连接器来实​​现。

公开(公告)号：US20120073867A1

公开(公告)日：2012-03-29

申请号：US13313896

申请日：2011-12-07

Applicant: Chih-Peng Fan ,  Yen-Ti Chia

Inventor： Chih-Peng Fan ,  Yen-Ti Chia

IPC: H05K1/09 ,  H05K1/00

CPC classification number: H05K1/111 ,  H01L2224/16225 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/0574 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit structure suitable for being disposed on a carrier board. The circuit structure comprises a first patterned conductive layer, a second patterned conductive layer, and a solder mask. The first patterned conductive layer is disposed on the carrier board. The second patterned conductive layer is disposed on a part of the first patterned conductive layer. A part of the edge of the second patterned conductive layer and a part of the edge of the first patterned conductive layer are substantially coplanar. The patterned solder mask covers a part of the first patterned conductive layer and has at least one opening for exposing the second patterned conductive layer and a part of the first patterned conductive layer adjacent to the second patterned conductive layer.

Abstract translation: 适于布置在载板上的电路结构。 电路结构包括第一图案化导电层，第二图案化导电层和焊接掩模。 第一图案化导电层设置在载体板上。 第二图案化导电层设置在第一图案化导电层的一部分上。 第二图案化导电层的边缘的一部分和第一图案化导电层的边缘的一部分基本上共面。 图案化的焊接掩模覆盖第一图案化导电层的一部分并且具有用于暴露第二图案化导电层的至少一个开口和与第二图案化导电层相邻的第一图案化导电层的一部分。