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公开(公告)号：US20190114227A1
公开(公告)日：2019-04-18
申请号：US15831405
申请日：2017-12-05
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Yu-Siang Yang , Kuo-Hsin Lai
Abstract: A decoding method is provided according to an exemplary embodiment of the invention. The decoding method includes: reading a data set from at least two physical units of a rewritable non-volatile memory module by using at least one read voltage level; performing a first-type decoding operation for first data by using the data set and recording decoding information of the first-type decoding operation if the data set conforms to a default condition; adjusting reliability information corresponding to the first data according to the recorded decoding information, and the reliability information is not used in the first-type decoding operation, and the adjusted reliability information is different from default reliability information corresponding to the first data; and performing a second-type decoding operation for the first data according to the adjusted reliability information.
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公开(公告)号：US11809706B2
公开(公告)日：2023-11-07
申请号：US17349918
申请日：2021-06-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Siang Yang , Yu-Cheng Hsu , Tsai-Hao Kuo , Wei Lin , An-Cheng Liu
IPC: G06F3/06
CPC classification number: G06F3/0604 , G06F3/0619 , G06F3/0655 , G06F3/0679
Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.
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公开(公告)号：US11561719B2
公开(公告)日：2023-01-24
申请号：US17242240
申请日：2021-04-27
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Siang Yang , Wei Lin , An-Cheng Liu , Yu-Heng Liu , Chun-Hsi Lai , Ting-Chien Zhan
IPC: G06F3/06
Abstract: A flash memory control method, a flash memory storage device and a flash memory controller are provided. The method includes the following. A flash memory module is instructed to perform a data merge operation to copy first data in a first physical unit into at least one second physical unit. After the first data is copied and before the first physical unit is erased, another programming operation is performed on the first physical unit to change a data storage state of at least a part of memory cells in the first physical unit from a first state into a second state. After the first physical unit is programmed, an erase operation is performed on the first physical unit.
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公开(公告)号：US20210397347A1
公开(公告)日：2021-12-23
申请号：US16921874
申请日：2020-07-06
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Hsiao-Yi Lin , Yu-Siang Yang
IPC: G06F3/06
Abstract: A data protection method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes, and the plurality of disk array tags corresponding to one of the word lines connected to one of the memory planes are at least partially identical to the plurality of disk array tags corresponding to another one of the word lines connected to another one of the memory planes; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.
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公开(公告)号：US10923212B2
公开(公告)日：2021-02-16
申请号：US16251105
申请日：2019-01-18
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , An-Cheng Liu , Yu-Cheng Hsu , Yu-Siang Yang
Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.
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Patent Agency Ranking
公开(公告)号：US20200379654A1
公开(公告)日：2020-12-03
申请号：US16529807
申请日：2019-08-02
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Hsiao-Yi Lin , Yu-Siang Yang
Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.
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公开(公告)号：US20190318791A1
公开(公告)日：2019-10-17
申请号：US16003114
申请日：2018-06-08
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , An-Cheng Liu , Szu-Wei Chen , Yu-Siang Yang
Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: programming first data into a plurality of first memory cells in the rewritable non-volatile memory module, such that the programmed first memory cells have a plurality of states; sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level; obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence; and adjusting the first read voltage level according to the first count information and default count information corresponding to the first read voltage level.
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公开(公告)号：US10424391B2
公开(公告)日：2019-09-24
申请号：US15811695
申请日：2017-11-14
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Szu-Wei Chen , Yu-Siang Yang
IPC: G11C29/00 , G11C29/52 , G11C16/10 , G06F12/02 , G06F11/10 , G11C16/30 , G11C16/08 , G11C16/26 , G11C11/56 , G11C16/04
Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: when first data is read from a first upper physical programming unit of a first physical programming unit group by using a second voltage selected from a first read voltage group, and a first error bit count of the first data is not greater than a first error bit count threshold, recording the second voltage; when a second data is read from a first lower physical programming unit of a second physical programming unit group by using a fourth voltage selected from a second read voltage group, and a second error bit count of the second data is not greater than a second error bit count threshold, recording the fourth voltage; generating a lookup table according to the second voltage and the fourth voltage; and performing a decoding operation according to the lookup table.
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公开(公告)号：US20240152296A1
公开(公告)日：2024-05-09
申请号：US18077190
申请日：2022-12-07
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Heng Liu , Yu-Siang Yang , An-Cheng Liu , Wei Lin
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0659 , G06F3/0679
Abstract: A data reading method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: receiving a read command from a host system, and the read command instructs reading data from at least one logical unit, and the logical unit is mapped to a first physical unit; obtaining state information of at least two neighboring memory cells in the first physical unit; determining an electrical parameter offset value corresponding to the neighboring memory cells according to the state information; and sending a read command sequence according to the electrical parameter offset value, and the read command sequence instructs reading the first physical unit based on at least one electrical parameter, and the electrical parameter is controlled by the electrical parameter offset value.
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公开(公告)号：US11615848B2
公开(公告)日：2023-03-28
申请号：US17214958
申请日：2021-03-29
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Siang Yang , Wei Lin , An-Cheng Liu , Yu-Heng Liu , Chun-Hsi Lai , Ting-Chien Zhan
Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: programming multiple first memory cells in a first physical erasing unit in a rewritable non-volatile memory module; and applying an electronic pulse to at least one word line in the rewritable non-volatile memory module. The at least one word line is coupled to multiple second memory cells in the first physical erasing unit. The second memory cells include the first memory cells. The electronic pulse is not configured to read, program, or erase the second memory cells.
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