-
公开(公告)号：US11543471B2
公开(公告)日：2023-01-03
申请号：US16466281
申请日：2017-12-04
Applicant: Purdue Research Foundation
Inventor： Kaushik Roy , Byunghoo Jung
Abstract: A current sensing system, comprising at least one magnetic tunnel junction device placed adjacent to a current carrying conductor electrically connected to a battery of a vehicle. The magnetic tunnel junction device is configured to measure a magnetic field around the conductor. A monitoring device is operatively connected to the magnetic tunnel junction device, wherein the monitoring device is configured to receive the magnetic field measurement and determine an estimate of the current flowing through the conductor.
-
公开(公告)号：US20190220412A1
公开(公告)日：2019-07-18
申请号：US16362672
申请日：2019-03-24
Applicant: Purdue Research Foundation
Inventor： Ashish Ranjan , Swagath Venkataramani , Zoha Pajouhi , Rangharajan Venkatesan , Kaushik Roy , Anand Raghunathan
IPC: G06F12/0846 , G06F12/0891
CPC classification number: G06F12/0848 , G06F12/0238 , G06F12/0846 , G06F12/0864 , G06F12/0891 , G06F2212/1028 , G06F2212/604 , G06F2212/621 , G11C11/16 , G11C11/1673 , G11C11/1675
Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.
-
公开(公告)号：US10073733B1
公开(公告)日：2018-09-11
申请号：US15693661
申请日：2017-09-01
Applicant: Purdue Research Foundation
Inventor： Shubham Jain , Ashish Ranjan , Kaushik Roy , Anand Raghunathan
CPC classification number: G06F11/1016 , G06F11/1012 , G06F11/1044 , G06F11/108
Abstract: A memory capable of carrying out compute-in-memory (CiM) operations is disclosed. The memory includes a matrix of bit cells having a plurality of bit cells along one or more rows and a plurality of bit cells along one or more columns, each bit cell having a value stored therein, an address decoder configured to receive addresses and activate two or more of the rows associated with the addresses, and a sensing circuit coupled to each column of bit cells, and configured to provide two or more outputs, wherein each output is associated with at least one compute operation performed on values stored in the bit cells in the column.
-
公开(公告)号：US20230341446A1
公开(公告)日：2023-10-26
申请号：US17779468
申请日：2020-09-30
Applicant: Purdue Research Foundation
Inventor： Kaushik Roy , Byunghoo Jung , Chamika Mihiranga Liyanagedera
IPC: G01R21/133 , G01R21/06 , G01R21/00
CPC classification number: G01R21/1331 , G01R21/06 , G01R21/006
Abstract: A system may include a non-intrusive sensor circuitry configured to provide electrical measurement data, including, for example, current data, voltage data, power factor data, active power consumption data, reactive power consumption data, or a combination thereof. A transient event detector may sweep the electrical measurement data with a first window and a second window, the first window adjacent to the second window. The transient event detector may identify a start and end of transient activity based on electrical measurement data referenced by separate adjacent windows. The transient event detector may capture a transient activity data segment comprising a portion of the electrical measurement data between first index and the second index.
-
15.发明公开公开(公告)号：US20230178125A1
公开(公告)日：2023-06-08
申请号：US17643215
申请日：2021-12-08
Applicant: Purdue Research Foundation
Inventor： Kaushik Roy , Amogh Agrawal , Mustafa Fayez Ahmed Ali , Indranil Chakraborty , Aayush Ankit , Utkarsh Saxena
CPC classification number: G11C7/16 , G11C7/1012 , G11C7/1063 , G11C7/109
Abstract: Sparsity-aware reconfiguration compute-in-memory (CIM) static random access memory (SRAM) systems are disclosed. In one aspect, a reconfigurable precision succession approximation register (SAR) analog-to-digital converter (ADC) that has the ability to form (n+m) bit precision using n-bit and m-bit sub-ADCs is provided. By controlling which sub-ADCs are used based on data sparsity, precision may be maintained as needed while providing a more energy efficient design.
-
Patent Agency Ranking
公开(公告)号：US20210117156A1
公开(公告)日：2021-04-22
申请号：US17071930
申请日：2020-10-15
Applicant: Purdue Research Foundation
Inventor： Mustafa Ali , Akhilesh Jaiswal , Kaushik Roy
Abstract: An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.
-
公开(公告)号：US20190258482A1
公开(公告)日：2019-08-22
申请号：US16265024
申请日：2019-02-01
Applicant: Purdue Research Foundation
Inventor： Akhilesh Ramlaut Jaiswal , Amogh Agrawal , Kaushik Roy
Abstract: An in-situ in-memory implication gate is disclosed. The gate include a memory cell. The cell includes a first voltage source, a second voltage source lower in value than the first voltage source, a first and second magnetic tunneling junction devices (MTJ) selectively juxtaposed in a series and mirror imaged relationship between the first and second sources, each having a pinned layer (PL) in a first direction and a free layer (FL) having a polarity that can be switched from the first direction in which case the MTJ is in a parallel configuration presenting an electrical resistance to current flow below a first resistance threshold to a second direction in which case the MTJ is in an anti-parallel configuration presenting an electrical resistance to current flow higher than a second resistance threshold, and further each having a non-magnetic layer (NML) separating the PL from the FL.
-
公开(公告)号：US09489618B2
公开(公告)日：2016-11-08
申请号：US14287701
申请日：2014-05-27
Applicant: Purdue Research Foundation
Inventor： Kaushik Roy , Mrigank Sharad
CPC classification number: H03K3/356104 , G06N3/063 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/54 , G11C13/0007 , G11C13/0069 , G11C15/02 , G11C15/046 , H03M1/38 , H03M1/46
Abstract: An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value. An enable circuit provides the enable signal if at least one of the one-shots is providing the first bit value. A neural network system includes a crossbar with row and column electrodes and resistive memory elements at their intersections. A writing circuit stores weights in the elements. A signal source applies signals to the row electrodes. Comparators compare signals on the column electrodes to corresponding references using domain-wall neurons and store bit values in CMOS latches by comparison with a threshold.
Abstract translation: 电子比较系统包括连续提供码字位的输入级。 连接到各个级的单次拍摄连续地提供第一比特值，直到与使能信号同时接收到具有非优选值的比特，然后提供第二不同的比特值。 如果单次拍摄中的至少一个提供第一比特值，则使能电路提供使能信号。 神经网络系统包括在其交点处具有行和列电极以及电阻存储器元件的交叉开关。 写入电路在元素中存储权重。 信号源将信号施加到行电极。 比较器使用畴壁神经元将列电极上的信号与相应的参考值进行比较，并通过与阈值进行比较将位锁定值存储在CMOS锁存器中。
-
公开(公告)号：US20150347896A1
公开(公告)日：2015-12-03
申请号：US14287701
申请日：2014-05-27
Applicant: Purdue Research Foundation
Inventor： Kaushik Roy , Mrigank Sharad
CPC classification number: H03K3/356104 , G06N3/063 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/54 , G11C13/0007 , G11C13/0069 , G11C15/02 , G11C15/046 , H03M1/38 , H03M1/46
Abstract: An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value. An enable circuit provides the enable signal if at least one of the one-shots is providing the first bit value. A neural network system includes a crossbar with row and column electrodes and resistive memory elements at their intersections. A writing circuit stores weights in the elements. A signal source applies signals to the row electrodes. Comparators compare signals on the column electrodes to corresponding references using domain-wall neurons and store bit values in CMOS latches by comparison with a threshold.
Abstract translation: 电子比较系统包括连续提供码字位的输入级。 连接到各个级的单次拍摄连续地提供第一比特值，直到与使能信号同时接收到具有非优选值的比特，然后提供第二不同的比特值。 如果单次拍摄中的至少一个提供第一比特值，则使能电路提供使能信号。 神经网络系统包括在其交点处具有行和列电极以及电阻存储器元件的交叉开关。 写入电路在元素中存储权重。 信号源将信号施加到行电极。 比较器使用畴壁神经元将列电极上的信号与相应的参考值进行比较，并通过与阈值进行比较将位锁定值存储在CMOS锁存器中。
-
公开(公告)号：US12253545B2
公开(公告)日：2025-03-18
申请号：US17779480
申请日：2020-11-24
Applicant: Purdue Research Foundation
Inventor： Kaushik Roy , Byunghoo Jung , Chamika Mihiranga Liyanagedera
Abstract: System and methods for high accuracy, non-intrusive current sensing are provided. A system may include two magnetic field sensors configured for differential sensing. The system may further include frontend circuitry configured to remove direct current (DC) offset of the magnetic field sensors, upconvert the outputs of the magnetic field sensors, and filter out at least one frequency component from the up-converted signals. The system may receive output signals from the front-end circuitry corresponding to each sensor. The system may further calculate a differential signal based on the output signals. The system may apply optimal detection based on the differential signal and a reference signal to calculate a measurement of current flow. The system may determine a phase angle measurement between the differential signal and the reference signal to calculate a direction of the current flow in the conductor and output various measurement information related to the detected current.
-
-
-
-
-
-
-
-
-
Search Results
37
records
(took 0.016 seconds)
