公开(公告)号：US11024535B2

公开(公告)日：2021-06-01

申请号：US16598772

申请日：2019-10-10

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  David O'Meara ,  Nicholas Joy ,  Gyanaranjan Pattanaik ,  Robert Clark ,  Kandabara Tapily ,  Takahiro Hakamata ,  Cory Wajda ,  Gerrit Leusink

IPC: H01L21/768

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

公开(公告)号：US20190393035A1

公开(公告)日：2019-12-26

申请号：US16447565

申请日：2019-06-20

Applicant: Tokyo Electron Limited

Inventor： David O'Meara ,  Lior Huli ,  Soo Doo Chae ,  Wan Jae Park

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311

Abstract: Methods are disclosed that selectively deposit a protective material on the top regions of patterned photoresist layers, such patterned EUV photoresist layers, to provide a protective cap that reduces erosion damage during etch processes used for pattern transfer. Some deposition of the protective material on the sidewalls of the patterned photoresist layer is acceptable, and any deposition of the protective material on the underlying layer below the patterned photoresist layer is preferably thinner than the deposition at the top of the photoresist pattern. Further, the selective deposition of protective caps can be implemented, for example, through the application of high-rotation speeds to spatial atomic layer deposition (ALD) techniques. The selective deposition of protective caps increases the flexibility of options to improve etch resistance for various processes/materials.

公开(公告)号：US11823910B2

公开(公告)日：2023-11-21

申请号：US16944563

申请日：2020-07-31

Applicant: Tokyo Electron Limited

Inventor： David O'Meara ,  Anthony Dip ,  Masanobu Igeta

IPC: H01L21/3105 ,  C23C16/458 ,  C23C16/455

CPC classification number: H01L21/31055 ,  C23C16/4584 ,  C23C16/45553

Abstract: Methods are provided for planarizing a patterned substrate in a spatial atomic layer processing system comprising a rotating platen. The patterned substrate may generally include features having higher regions and lower regions. To planarize the patterned substrate, or reduce a height differential between the higher and lower regions, a selective atomic layer etching (ALE) process is disclosed to preferentially form a modified layer on the higher regions of the features by exposing a surface of the patterned substrate to a precursor gas while the rotating platen spins at a high rotational speed. By preferentially forming the modified layer on the higher regions of the features, and subsequently removing the modified layer, the selective ALE process described herein preferentially etches the higher regions of the features to lessen the height differential between the higher and lower regions until a desired planarization of the features is achieved.

公开(公告)号：US11742241B2

公开(公告)日：2023-08-29

申请号：US17487987

申请日：2021-09-28

Applicant: TOKYO ELECTRON LIMITED

Inventor： Xinghua Sun ,  Yen-Tien Lu ,  Angelique Raley ,  David O'Meara ,  Jeffrey Smith

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027 ,  H01L21/3205

CPC classification number: H01L21/76897 ,  H01L21/0228 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/32056 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831

Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

公开(公告)号：US11651967B2

公开(公告)日：2023-05-16

申请号：US17514233

申请日：2021-10-29

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  David O'Meara ,  Andrew Metz ,  Yun Han

IPC: H01L21/306 ,  H01L21/3065 ,  H01L21/033 ,  H01J37/305 ,  H01J37/32 ,  H01L21/02

CPC classification number: H01L21/3065 ,  H01J37/3053 ,  H01J37/32082 ,  H01L21/02115 ,  H01L21/0337

Abstract: Improved process flows and methods are provided herein for forming a passivation layer on sidewall surfaces of openings formed in an amorphous carbon layer (ACL) to avoid bowing during an ACL etch process. More specifically, improved process flows and methods are provided to form a silicon-containing passivation layer on sidewall surfaces of the openings created within the ACL without utilizing atomic layer deposition (ALD) techniques or converting the silicon-containing passivation layer to an oxide or a nitride. As such, the improved process flows and methods disclosed herein may be used to protect the sidewall surfaces of the ACL and prevent bowing during the ACL etch process, while also reducing processing time and improving throughput.

公开(公告)号：US11621164B2

公开(公告)日：2023-04-04

申请号：US17014515

申请日：2020-09-08

Applicant: Tokyo Electron Limited

Inventor： Katie Lutker-Lee ,  David O'Meara ,  Angelique Raley

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/02

Abstract: Improved process flows and methods are provided herein for trimming structures formed on a patterned substrate. In the disclosed process flows and methods, a self-aligned multiple patterning (SAMP) process is utilized for patterning structures, such as mandrels, on a substrate. After the structures are patterned, an atomic layer deposition (ALD) process is used to form a spacer layer on the patterned structures. In the SAMP process disclosed herein, a critical dimension (CD) of the patterned structures is trimmed concurrently with, and as a result of, the formation of the spacer layer by controlling various ALD process parameters and conditions. By trimming the patterned structures in situ of the ALD chamber used to form the spacer layer on the patterned structures, the improved process flows and methods described herein provide a CD trim method that does not adversely affect the pattern profile or process throughput.

公开(公告)号：US10978307B2

公开(公告)日：2021-04-13

申请号：US16938049

申请日：2020-07-24

Applicant: Tokyo Electron Limited

Inventor： David O'Meara ,  Eric Chih-Fang Liu ,  Richard Farrell ,  Soo Doo Chae

IPC: H01L21/3065 ,  H01L21/033 ,  H01L21/02

Abstract: A method of patterning a substrate includes receiving a substrate having microfabricated structures, including mandrels; executing a deposition process that deposits a first material on the mandrels, the deposition process including cyclically moving the substrate through a set of deposition modules. The substrate is moved through the set of deposition modules so that the first material is deposited at a first thickness at top portions of the mandrels and at a second thickness at bottom portions of mandrels, the first thickness being greater than the second thickness. The method includes executing a spacer deposition process that conformally deposits a second material on the substrate; executing a spacer open etch that removes depositions of the second material from over a top surface of the mandrels; removing the first material and the mandrels from the substrate, leaving sidewall spacers; and transferring a pattern defined by the sidewall spacers into an underlying layer.

公开(公告)号：US20210057226A1

公开(公告)日：2021-02-25

申请号：US16938049

申请日：2020-07-24

Applicant: Tokyo Electron Limited

Inventor： David O'Meara ,  Eric Chih-Fang Liu ,  Richard Farrell ,  Soo Doo Chae

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/033

Abstract: A method of patterning a substrate includes receiving a substrate having microfabricated structures, including mandrels; executing a deposition process that deposits a first material on the mandrels, the deposition process including cyclically moving the substrate through a set of deposition modules. The substrate is moved through the set of deposition modules so that the first material is deposited at a first thickness at top portions of the mandrels and at a second thickness at bottom portions of mandrels, the first thickness being greater than the second thickness. The method includes executing a spacer deposition process that conformally deposits a second material on the substrate; executing a spacer open etch that removes depositions of the second material from over a top surface of the mandrels; removing the first material and the mandrels from the substrate, leaving sidewall spacers; and transferring a pattern defined by the sidewall spacers into an underlying layer.

公开(公告)号：US10770294B2

公开(公告)日：2020-09-08

申请号：US16447565

申请日：2019-06-20

Applicant: Tokyo Electron Limited

Inventor： David O'Meara ,  Lior Huli ,  Soo Doo Chae ,  Wan Jae Park

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311

Abstract: Methods are disclosed that selectively deposit a protective material on the top regions of patterned photoresist layers, such patterned EUV photoresist layers, to provide a protective cap that reduces erosion damage during etch processes used for pattern transfer. Some deposition of the protective material on the sidewalls of the patterned photoresist layer is acceptable, and any deposition of the protective material on the underlying layer below the patterned photoresist layer is preferably thinner than the deposition at the top of the photoresist pattern. Further, the selective deposition of protective caps can be implemented, for example, through the application of high-rotation speeds to spatial atomic layer deposition (ALD) techniques. The selective deposition of protective caps increases the flexibility of options to improve etch resistance for various processes/materials.

公开(公告)号：US20190355617A1

公开(公告)日：2019-11-21

申请号：US16415687

申请日：2019-05-17

Applicant: Tokyo Electron Limited

Inventor： David O'Meara ,  Angelique Raley ,  Xinghua Sun ,  Yen-Tien Lu

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/762

Abstract: An atomic layer deposition (ALD) technique is used to deposit one or more layers on hard mask layers and the sidewalls of low-K dielectric trench as part of the trench etch process. The ALD layer(s) can prevent the hard mask from being eroded during various hard mask open processes. Further, the ALD layer(s) may be utilized to prevent the low-K dielectric sidewall from being laterally etched during the low-K dielectric trench etch. Hence, better control of the trench profile and better critical dimension control may be provided.