公开(公告)号：US20220189764A1

公开(公告)日：2022-06-16

申请号：US17653252

申请日：2022-03-02

Applicant: Tokyo Electron Limited

Inventor： Michael Edley ,  Xinghua Sun ,  Yen-Tien Lu ,  Angelique Raley ,  Henan Zhang ,  Hiroyuki Suzuki ,  Shan Hu

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/67

Abstract: A method for processing a substrate includes performing a first etch process to form a plurality of partial features in a dielectric layer disposed over the substrate; performing an irradiation process to irradiate the substrate with ultra-violet radiation having a wavelength between 100 nm and 200 nm; and after the irradiation process, performing a second etch process to form a plurality of features from the plurality of partial features.

公开(公告)号：US11289325B2

公开(公告)日：2022-03-29

申请号：US17180077

申请日：2021-02-19

Applicant: Tokyo Electron Limited

Inventor： Michael Edley ,  Xinghua Sun ,  Yen-Tien Lu ,  Angelique Raley ,  Henan Zhang ,  Hiroyuki Suzuki ,  Shan Hu

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/67

Abstract: A method for processing a substrate includes performing a first etch process to form a plurality of partial features in a dielectric layer disposed over the substrate; performing an irradiation process to irradiate the substrate with ultra-violet radiation having a wavelength between 100 nm and 200 nm; and after the irradiation process, performing a second etch process to form a plurality of features from the plurality of partial features.

公开(公告)号：US20210407790A1

公开(公告)日：2021-12-30

申请号：US17180077

申请日：2021-02-19

Applicant: Tokyo Electron Limited

Inventor： Michael Edley ,  Xinghua Sun ,  Yen-Tien Lu ,  Angelique Raley ,  Henan Zhang ,  Hiroyuki Suzuki ,  Shan Hu

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/67

Abstract: A method for processing a substrate includes performing a first etch process to form a plurality of partial features in a dielectric layer disposed over the substrate; performing an irradiation process to irradiate the substrate with ultra-violet radiation having a wavelength between 100 nm and 200 nm; and after the irradiation process, performing a second etch process to form a plurality of features from the plurality of partial features.

公开(公告)号：US20210265164A1

公开(公告)日：2021-08-26

申请号：US16851414

申请日：2020-04-17

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Akiteru Ko ,  Angelique Raley ,  Henan Zhang ,  Shan Hu ,  Subhadeep Kal

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/306

Abstract: In certain embodiments, a method of forming a semiconductor device includes forming a patterned resist layer over a hard mask layer using an extreme ultraviolet (EUV) lithography process. The hard mask layer is disposed over a substrate. The method includes patterning the hard mask layer using the patterned resist layer as an etch mask. The method includes smoothing the hard mask layer by forming, using a first atomic layer etch step, a first layer by converting a first portion of the hard mask layer, and by removing, using a second atomic layer etch step, the first layer.

公开(公告)号：US20210242089A1

公开(公告)日：2021-08-05

申请号：US16781078

申请日：2020-02-04

Applicant: Tokyo Electron Limited

Inventor： Yun Han ,  Andrew Metz ,  Xinghua Sun ,  David L. O'Meara ,  Kandabara Tapily ,  Henan Zhang ,  Shan Hu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L27/088

Abstract: In one embodiment, a method includes providing a substrate comprising a source/drain contact region and a dummy gate, forming a first etch stop layer aligned to the source/drain contact region, where the first etch stop layer does not cover the dummy gate. The method may include forming a second etch stop layer over the first etch stop layer, the second etch stop layer covering the first etch stop layer and the dummy gate. The method may include converting the dummy gate to a metal gate. The method may include removing the second etch stop layer using a plasma etching process. The method may include removing the first etch stop layer.

公开(公告)号：US12288698B2

公开(公告)日：2025-04-29

申请号：US18112120

申请日：2023-02-21

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Peter D'Elia

IPC: H01L21/67 ,  H01L21/02 ,  H01L21/687

Abstract: Improved puddle processes and methods are provided herein for retaining a processing liquid on a surface of a semiconductor substrate. More specifically, improved methods are provided herein for retaining a puddle within a center region of a semiconductor substrate while the substrate is stationary, or rotating at relatively low rotational speeds. In the disclosed embodiments, a puddle is retained within a center region of the semiconductor substrate by a thin film, which is deposited within a peripheral edge region of the substrate before a processing liquid is dispensed within the center region of the substrate to form the puddle.

公开(公告)号：US12243749B2

公开(公告)日：2025-03-04

申请号：US17952613

申请日：2022-09-26

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Henan Zhang ,  Sangita Kumari ,  Peter Delia

IPC: H01L21/306

Abstract: Embodiments of a wet etch process and methods are disclosed herein to provide uniform wet etching of material within high aspect ratio features. In the present disclosure, a wet etch process is used to etch material within high aspect ratio features, such as deep trenches and holes, provided on a patterned substrate. Uniform wet etching is provided in the present disclosure by ensuring that wall surfaces of the material being etched (or wall surfaces adjacent to the material being etched) exhibit a neutral surface charge when exposed to the etch solution used to etch the material.

公开(公告)号：US20240399422A1

公开(公告)日：2024-12-05

申请号：US18806852

申请日：2024-08-16

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Peter D'Elia ,  Ronald Nasman

IPC: B08B3/02 ,  B08B13/00 ,  F26B5/00 ,  H01L21/02 ,  H01L21/67

Abstract: Improved processing systems and methods are provided for wet and dry processing of a semiconductor wafer. Provided is an enclosed chamber for processing a semiconductor wafer within a processing space and a drainage system for directing processing fluids out of the processing space. The enclosed chamber includes a top plate and a bottom plate, which physically confine the processing fluids within a relatively small, enclosed processing space. This forces the processing fluids to flow radially across the wafer surface(s) without the need to rotate the wafer. The drainage system contains a conduit that is downstream from the processing space and configured to retain a portion of a processing fluid dispensed within the processing space. The portion retained within the conduit provides a pressure resistance against the processing fluid(s) dispensed within the processing space to improve wet and dry processing of the wafer surfaces.

公开(公告)号：US12103052B2

公开(公告)日：2024-10-01

申请号：US18192279

申请日：2023-03-29

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Peter D'Elia ,  Ronald Nasman

IPC: B08B3/02 ,  B08B13/00 ,  F26B5/00 ,  H01L21/02 ,  H01L21/67

CPC classification number: B08B3/02 ,  B08B13/00 ,  F26B5/005 ,  H01L21/02057 ,  H01L21/67028 ,  B08B2203/007

Abstract: Improved processing systems and methods are provided for wet and dry processing of a semiconductor wafer. Provided is an enclosed chamber for processing a semiconductor wafer within a processing space and a drainage system for directing processing fluids out of the processing space. The enclosed chamber includes a top plate and a bottom plate, which physically confine the processing fluids within a relatively small, enclosed processing space. This forces the processing fluids to flow radially across the wafer surface(s) without the need to rotate the wafer. The drainage system contains a conduit that is downstream from the processing space and configured to retain a portion of a processing fluid dispensed within the processing space. The portion retained within the conduit provides a pressure resistance against the processing fluid(s) dispensed within the processing space to improve wet and dry processing of the wafer surfaces.

公开(公告)号：US12100599B2

公开(公告)日：2024-09-24

申请号：US17942359

申请日：2022-09-12

Applicant: Tokyo Electron Limited

Inventor： Shan Hu ,  Henan Zhang ,  Sangita Kumari ,  Peter Delia

IPC: H01L21/311 ,  H01L21/306 ,  H01L21/3213

CPC classification number: H01L21/31111 ,  H01L21/30604 ,  H01L21/32134

Abstract: Embodiments of a wet etch process and method are disclosed to provide uniform etching of material formed within features (such as, e.g., trenches, holes, slits, etc.) having different critical dimension (CD). By combining a non-aqueous organic-based etch solution and an aqueous-based etch solution (either in series or in parallel) within a wet etch process, the disclosed embodiments utilize the opposing effects of CD-dependent etching to provide uniform etching of the material, regardless of CD.