公开(公告)号：US20210159191A1

公开(公告)日：2021-05-27

申请号：US17170736

申请日：2021-02-08

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju LIN ,  Cheng-Ta KO ,  Yu-Hua CHEN ,  Tzyy-Jang TSENG ,  Ra-Min TAIN

IPC: H01L23/00 ,  H01L23/66 ,  H01L23/16

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

公开(公告)号：US20200266155A1

公开(公告)日：2020-08-20

申请号：US16866530

申请日：2020-05-04

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju LIN ,  Cheng-Ta KO ,  Yu-Hua CHEN ,  Tzyy-Jang TSENG ,  Ra-Min TAIN

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/66

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

公开(公告)号：US20200235272A1

公开(公告)日：2020-07-23

申请号：US16842716

申请日：2020-04-07

Applicant: Unimicron Technology Corp.

Inventor： Pei-Wei WANG ,  Cheng-Ta KO ,  Yu-Hua CHEN ,  De-Shiang LIU ,  Tzyy-Jang TSENG

IPC: H01L33/62

Abstract: A manufacturing method of a light emitting device package structure is provided. The method includes following operations: (i) providing a circuit redistribution structure; (ii) providing a first substrate; (iii) forming a circuit layer structure over the first substrate, wherein the circuit layer structure includes a first circuit layer; (iv) before or after operation (iii), placing a light emitting device between the first substrate and the circuit layer structure or over the circuit layer structure, wherein the light emitting device is electrically connected with the first circuit layer; and (v) placing the circuit redistribution structure over the light emitting device, wherein the circuit redistribution structure includes a first redistribution layer, a second redistribution layer, and a chip, and the first redistribution layer includes a second circuit layer and a conductive contact that contacts the second circuit layer.

公开(公告)号：US20200006610A1

公开(公告)日：2020-01-02

申请号：US16140563

申请日：2018-09-25

Applicant: Unimicron Technology Corp.

Inventor： Pei-Wei WANG ,  Cheng-Ta KO ,  Yu-Hua CHEN ,  De-Shiang LIU ,  Tzyy-Jang TSENG

IPC: H01L33/62

Abstract: A light emitting device package structure includes a substrate, a circuit layer structure, a light emitting device, a first redistribution layer, a conductive connector, a second redistribution layer, and a chip. The circuit layer structure is disposed over the substrate, and the circuit layer structure includes a first circuit layer. The light emitting device is disposed over the circuit layer structure and is electrically connected with the first circuit layer. The first redistribution layer is disposed over the light emitting device and includes a second circuit layer and a conductive contact contacting the second circuit layer. The conductive connector connects the first circuit layer and the second circuit layer. The second redistribution layer is disposed over the first redistribution layer and includes a third circuit layer contacting the conductive contact. The chip is disposed over the second redistribution layer and is electrically connected with the third circuit layer.

公开(公告)号：US20180122733A1

公开(公告)日：2018-05-03

申请号：US15853926

申请日：2017-12-25

Applicant: Unimicron Technology Corp.

Inventor： Yu-Hua CHEN ,  Cheng-Ta KO

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/096 ,  H05K2201/10378

Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.

公开(公告)号：US20180014404A1

公开(公告)日：2018-01-11

申请号：US15273672

申请日：2016-09-22

Applicant: Unimicron Technology Corp.

Inventor： Yu-Chung HSIEH ,  Chun-Hsien CHIEN ,  Wei-Ti LIN ,  Yu-Hua CHEN

IPC: H05K1/03 ,  H05K1/02

CPC classification number: H05K1/0306 ,  H05K1/0271 ,  H05K3/0052 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/068 ,  H05K2201/09845

Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.