公开(公告)号：US11932531B2

公开(公告)日：2024-03-19

申请号：US17694083

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Jung Chen

IPC: B81B3/00 ,  B81C1/00 ,  G02B7/02 ,  H04N23/54 ,  H04N23/68

CPC classification number: B81B3/0072 ,  B81C1/00666 ,  H04N23/54 ,  H04N23/687 ,  B81B2203/0118 ,  B81B2203/019 ,  B81B2203/0307 ,  B81C2201/0105 ,  B81C2201/0178 ,  G02B7/021

Abstract: The present disclosure relates to an integrated chip structure including a MEMS actuator. The MEMS actuator includes an anchor having a first plurality of branches extending outward from a central region of the anchor. The first plurality of branches respectively include a first plurality of fingers. A proof mass surrounds the anchor and includes a second plurality of branches extending inward from an interior sidewall of the proof mass. The second plurality of branches respectively include a second plurality of fingers interleaved with the first plurality of fingers as viewed in a top-view. One or more curved cantilevers are coupled between the proof mass and a frame wrapping around the proof mass. The one or more curved cantilevers have curved outer surfaces having one or more inflection points as viewed in the top-view.

公开(公告)号：US20230219806A1

公开(公告)日：2023-07-13

申请号：US17694083

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Jung Chen

IPC: B81B3/00 ,  B81C1/00 ,  H04N5/225 ,  H04N5/232

CPC classification number: B81B3/0072 ,  B81C1/00666 ,  H04N5/2253 ,  H04N5/23287 ,  B81B2203/0118 ,  B81B2203/019 ,  B81B2203/0307 ,  B81C2201/0105 ,  B81C2201/0178 ,  G02B7/021

Abstract: The present disclosure relates integrated chip structure including a MEMS actuator. The MEMS actuator includes an anchor having a first plurality of branches extending outward from a central region of the anchor. The first plurality of branches respectively include a first plurality of fingers. A proof mass surrounds the anchor and includes a second plurality of branches extending inward from an interior sidewall of the proof mass. The second plurality of branches respectively include a second plurality of fingers interleaved with the first plurality of fingers as viewed in a top-view. One or more curved cantilevers are coupled between the proof mass and a frame wrapping around the proof mass. The one or more curved cantilevers have curved outer surfaces having one or more inflection points as viewed in the top-view.

公开(公告)号：US11673798B2

公开(公告)日：2023-06-13

申请号：US17084389

申请日：2020-10-29

Applicant: International Business Machines Corporation ,  THE UNIVERSITY OF BASEL

Inventor： Gabriel Fernando Puebla Hellmann ,  Diego Monserrat Lopez ,  Ute Drechsler ,  Marcel Mayor ,  Emanuel Marc Löertscher

IPC: B81C1/00 ,  B81B1/00 ,  B01L3/00

CPC classification number: B81C1/00119 ,  B01L3/502707 ,  B01L3/502715 ,  B81B1/002 ,  B01L2200/12 ,  B01L2300/12 ,  B01L2300/168 ,  B81B2201/058 ,  B81B2203/0353 ,  B81B2203/04 ,  B81C2201/0132 ,  B81C2201/0159 ,  B81C2201/0178

Abstract: A device includes a first layer of an electrically insulating material and a second layer of a non-electrically insulating material (e.g., semiconductor or electrically conductive) extending on the first layer. The second layer is structured so as to define opposite, lateral walls of a microchannel, a bottom wall of which is defined by an exposed surface of the first layer. The second layer is further structured to form one or more electrical insulation barriers; each barrier includes a line of through holes, each surrounded by an oxidized region of the material of the second layer. The through holes alternate with oxidized portions of the oxidized region along the line. Each barrier extends, as a whole, laterally across the second layer up to one of the lateral walls and delimits two sections of the second layer on each side of the barrier and on a same side of the microchannel.

公开(公告)号：US11667524B2

公开(公告)日：2023-06-06

申请号：US17130335

申请日：2020-12-22

Applicant: HYUNDAI KEFICO CORPORATION

Inventor： Jun Hwan Choi ,  Chi Yeon Kim

IPC: B81C1/00 ,  G01L19/06

CPC classification number: B81C1/00357 ,  B81C2201/0133 ,  B81C2201/0176 ,  B81C2201/0178 ,  B81C2201/0195 ,  G01L19/0654

Abstract: Disclose is a method for fabricating a semiconductor device. The method includes: forming a groove such as by etching one side surface of a first substrate; attaching a second substrate including a silicon layer on the etched surface of the first substrate formed with the hollow groove; etching the second substrate so as to leave substantially only the silicon layer; forming a thin film structure on the surface of silicon layers of the second substrate; and separating the second substrate formed with the thin film structure from the first substrate. For example, the groove structure may be formed in the lower portion of the device in the process of fabricating the semiconductor device to facilitate the final device separation.

公开(公告)号：US20170166438A1

公开(公告)日：2017-06-15

申请号：US14969329

申请日：2015-12-15

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0056 ,  B81B2201/012 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/0015 ,  B81C1/00619 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0178 ,  B81C2203/0109 ,  B81C2203/0136 ,  H01H59/0009 ,  H01H2001/0078

Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

公开(公告)号：US08415220B2

公开(公告)日：2013-04-09

申请号：US12709981

申请日：2010-02-22

Applicant: Tymon Barwicz

Inventor： Tymon Barwicz

IPC: H01L21/336

CPC classification number: H01L29/0665 ,  B81B2203/0109 ,  B81C1/00833 ,  B81C2201/0178 ,  B81C2201/053 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

Abstract: Techniques for preventing bending/buckling of suspended micro/nanostructures during oxidation are provided. In one aspect, a method for oxidizing a structure is provided. The method includes providing the structure having at least one suspended element selected from the group consisting of: a microstructure, a nanostructure and a combination thereof; surrounding the at least one suspended element in a cladding material; and oxidizing the at least one suspended element through the cladding material, wherein the cladding material physically constrains and thereby prevents distortion of the at least one suspended element during the oxidation.

Abstract translation: 提供了用于在氧化期间防止悬浮的微/纳米结构的弯曲/屈曲的技术。 一方面，提供一种氧化结构的方法。 该方法包括提供具有至少一个悬浮元素的结构，所述悬浮元素选自：微结构，纳米结构及其组合; 围绕包层材料中的至少一个悬挂元件; 以及通过所述包层材料氧化所述至少一个悬浮元件，其中所述包层材料物理地约束并由此防止所述至少一个悬浮元件在氧化期间的变形。

公开(公告)号：US20120021550A1

公开(公告)日：2012-01-26

申请号：US13176371

申请日：2011-07-05

Applicant: CHRISTEL DIEPPEDALE ,  STEPHAN BOREL ,  BRUNO REIG ,  HENRI SIBUET

Inventor： CHRISTEL DIEPPEDALE ,  STEPHAN BOREL ,  BRUNO REIG ,  HENRI SIBUET

IPC: H01L21/02

CPC classification number: B81C1/00158 ,  B81B2201/018 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2203/0361 ,  B81C1/00492 ,  B81C2201/0178 ,  H01H1/0036

Abstract: The fabrication of a semiconductor fixed structure defining a volume, for example of a MEMS micro electro-mechanical system includes, determining thicknesses beforehand depending on the functional distances associated with elements. At least one element is formed on a substrate by thermal oxidation of the substrate so as to form an oxide layer followed by selective etching of the oxide layer so as to define the volume in an etched portion by baring the underlying substrate so as to define the element in an unetched portion, and later oxidation of the substrate so as to form an oxide layer, in order to obtain the elements at the functional distances.

Abstract translation: 限定体积的半导体固定结构（例如MEMS微机电系统）的制造包括：根据与元件相关联的功能距离预先确定厚度。 通过衬底的热氧化在衬底上形成至少一个元件，以便形成氧化物层，然后选择性地蚀刻氧化物层，以便通过掩埋下面的衬底限定蚀刻部分中的体积，从而限定 元素在未蚀刻部分中，并且随后氧化基底以形成氧化物层，以便在功能距离处获得元件。

公开(公告)号：US07862731B2

公开(公告)日：2011-01-04

申请号：US10527789

申请日：2003-09-12

Applicant: Matthias Aikele ,  Albert Engelhardt ,  Marcus Frey ,  Bernhard Schmid ,  Helmut Seidel

Inventor： Matthias Aikele ,  Albert Engelhardt ,  Marcus Frey ,  Bernhard Schmid ,  Helmut Seidel

IPC: H01L21/302 ,  B81C1/00

CPC classification number: B81C1/00698 ,  B81B2201/0235 ,  B81B2203/033 ,  B81C2201/0178

Abstract: To form an isolation structure in a semiconductor substrate, at least two trenches are formed with a rib therebetween in the semiconductor substrate, and then the semiconductor material in the area of the trenches and particularly the rib is converted to an electrically insulating material. For example, this is accomplished by thermal oxidation of silicon semiconductor material of the rib.

Abstract translation: 为了在半导体衬底中形成隔离结构，在半导体衬底中形成至少两个沟槽，其间沟槽中的半导体材料转变为电绝缘材料。 例如，这通过肋的硅半导体材料的热氧化来实现。

公开(公告)号：US20090176064A1

公开(公告)日：2009-07-09

申请号：US12225670

申请日：2007-03-28

Applicant: Takayuki Hirano ,  Nobuyuki Kawakami ,  Masato Kannaka

Inventor： Takayuki Hirano ,  Nobuyuki Kawakami ,  Masato Kannaka

IPC: B32B3/10 ,  B05D3/02 ,  B05D5/12 ,  C23C16/513 ,  H01L21/306

CPC classification number: G01F1/692 ,  B81B2201/0278 ,  B81B2203/0127 ,  B81C1/00666 ,  B81C2201/0169 ,  B81C2201/0178 ,  C23C16/402 ,  C23C16/56 ,  Y10T428/24488 ,  Y10T428/24612

Abstract: It is intended to provide a membrane structure element that can be easily manufactured, has an excellent insulating property and high quality; and a method for manufacturing the membrane structure element. The manufacturing method is for manufacturing a membrane structure element including a membrane formed of a silicon oxide film and a substrate which supports the membrane in a hollow state by supporting a part of a periphery of the membrane. The method includes: a film formation step of forming a heat-shrinkable silicon oxide film 13 on a surface of a silicon substrate 2 by plasma CVD method; a heat treatment step of performing a heat treatment to cause the thermal shrinkage of the silicon oxide film 13 formed on the substrate 1; and a removal step of removing a part of the substrate 2 in such a manner that a membrane-corresponding part of the silicon oxide film 13 is supported as a membrane in a hollow state with respect to the substrate 2 to form a recessed part 4.

Abstract translation: 本发明提供可以容易地制造，具有优异的绝缘性和高质量的膜结构元件; 和膜结构元件的制造方法。 该制造方法是用于制造包括由氧化硅膜形成的膜的膜结构元件和通过支撑膜的周边的一部分而将膜支撑在中空状态的基板。 该方法包括：通过等离子体CVD法在硅衬底2的表面上形成热收缩氧化硅膜13的成膜步骤; 对形成在基板1上的氧化硅膜13的热收缩进行热处理的热处理工序; 以及去除基板2的一部分的去除步骤，使得氧化硅膜13的膜相应部分作为相对于基板2的中空状态的膜被支撑以形成凹部4。

公开(公告)号：US20030224565A1

公开(公告)日：2003-12-04

申请号：US10342949

申请日：2003-01-15

Inventor： Khalil Najafi ,  Chunbo Zhang

IPC: H01L021/8238

CPC classification number: F28F13/185 ,  B81B2203/033 ,  B81C1/0038 ,  B81C2201/0132 ,  B81C2201/0178 ,  F28F2260/00 ,  H01L21/76208

Abstract: A method of fabricating a thick silicon dioxide layer without the need for long deposition or oxidation and a device having such a layer are provided. Deep reactive ion etching (DRIE) is used to create high-aspect ratio openings or trenches and microstructures or silicon pillars, which are then oxidized and/or refilled with LPCVD oxide or other deposited silicon oxide films to create layers as thick as the DRIE etched depth allows. Thickness in the range of 10-100 nullm have been achieved. Periodic stiffeners perpendicular to the direction of the trenches are used to provide support for the pillars during oxidation. The resulting SiO2 layer is impermeable and can sustain large pressure difference. Thermal tests show that such thick silicon dioxide diaphragms or layers can effectively thermally isolate heated structures from neighboring structures and devices within a distance of hundred of microns. Such SiO2 diaphragms or layers of thickness 50-60 nullm can sustain an extrinsic shear stress up to 3-5 Mpa. These thick insulating microstructures or layers can be used in thermal, mechanical, fluidic, optical, and bio microsystems.

Abstract translation: 提供了制造厚二氧化硅层而不需要长时间沉积或氧化的方法和具有这种层的器件。 深反应离子蚀刻（DRIE）用于产生高纵横比的开口或沟槽和微结构或硅柱，然后用LPCVD氧化物或其他沉积的氧化硅膜氧化和/或再填充以产生与DRIE蚀刻的厚度相同的层 深度允许。 已达到10-100mam范围内的厚度。 垂直于沟槽方向的周期性加强筋用于在氧化过程中为支柱提供支撑。 所得的SiO 2层是不渗透的并且可以承受较大的压力差。 热测试表明，这种厚的二氧化硅隔膜或层可以有效地将加热的结构与邻近的结构和器件隔离在一百微米的距离内。 这种厚度为50-60μm的SiO 2膜片或层可承受高达3-5Mpa的外在剪切应力。 这些厚的绝缘微结构或层可用于热，机械，流体，光学和生物微系统。