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    CMOS-MEMS INTEGRATED DEVICE WITH SELECTIVE BOND PAD PROTECTION
    13.
    发明申请
    CMOS-MEMS INTEGRATED DEVICE WITH SELECTIVE BOND PAD PROTECTION 审中-公开
    具有选择性焊盘保护的CMOS-MEMS集成器件

    公开(公告)号：US20170066648A1

    公开(公告)日：2017-03-09

    申请号：US15356916

    申请日：2016-11-21

    Applicant: INVENSENSE, INC.

    Inventor： Daesung LEE

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00801 ,  B81B7/0025 ,  B81B2207/07 ,  B81C2201/053 ,  B81C2203/0785

    Abstract: A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.

    Abstract translation: 公开了一种用于制备半导体晶片的方法和系统。 在第一方面，该方法包括在半导体晶片上的图案化顶部金属上提供钝化层，蚀刻钝化层以使用第一掩模打开半导体晶片中的接合焊盘，在半导体晶片上沉积保护层，图案化 使用第二掩模的保护层，并且使用第三掩模蚀刻钝化层以打开半导体晶片中的其它电极。 该系统包括MEMS器件，其还包括第一基底和与第一基底结合的第二基底，其中第二基底是通过上述方法的步骤制备的。

    METHOD OF PROCESSING WAFER
    14.
    发明申请
    METHOD OF PROCESSING WAFER 审中-公开
    加工方法

    公开(公告)号：US20170062278A1

    公开(公告)日：2017-03-02

    申请号：US15251283

    申请日：2016-08-30

    Applicant: DISCO Corporation

    Inventor： Karl Heinz Priewasser

    IPC: H01L21/78 ,  H01L21/56

    CPC classification number: H01L21/78 ,  B81C1/00825 ,  B81C1/00896 ,  B81C2201/053 ,  H01L21/304 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2224/11

    Abstract: The invention relates to a method of processing a wafer, having on one side a device area with a plurality of devices partitioned by a plurality of division lines and a peripheral marginal area having no devices and being formed around the device area, wherein the device area is formed with a plurality of protrusions protruding from a plane surface of the wafer. The method comprises attaching a protective film, for covering the devices on the wafer, to the one side of the wafer, wherein the protective film is adhered to at least a part of the one side of the wafer with an adhesive, and providing a carrier having a curable resin applied to a front surface thereof. The method further comprises attaching the one side of the wafer, having the protective film attached thereto, to the front surface of the carrier, so that the protrusions protruding from the plane surface of the wafer are embedded in the curable resin and a back surface of the carrier opposite to the front surface thereof is substantially parallel to the side of the wafer being opposite to the one side, and grinding the side of the wafer being opposite to the one side for adjusting the wafer thickness.

    Abstract translation: 本发明涉及一种处理晶片的方法，该方法在一侧具有由多个划分线划分的多个器件的器件区域和不具有器件的周边边缘区域，并且围绕器件区域形成，其中器件区域 形成有从晶片的平面突出的多个突起。 该方法包括将用于将晶片上的器件覆盖的保护膜附接到晶片的一侧，其中保护膜用粘合剂粘附到晶片的一侧的至少一部分，并且提供载体 具有施加到其前表面的可固化树脂。 该方法还包括将具有附着于其上的保护膜的晶片的一侧附接到载体的前表面，使得从晶片的平面表面突出的突起嵌入在可固化树脂中，并且背面 与其前表面相反的载体基本上平行于与一侧相对的晶片侧，并且研磨晶片的与该一侧相对的侧面以调整晶片厚度。

    Encapsulation structure including a mechanically reinforced cap and with a getter effect
    16.
    发明授权
    Encapsulation structure including a mechanically reinforced cap and with a getter effect 有权
    封装结构包括机械加强盖和吸气剂效应

    公开(公告)号：US09511991B2

    公开(公告)日：2016-12-06

    申请号：US14331285

    申请日：2014-07-15

    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

    Inventor： Xavier Baillin ,  Bernard Diem ,  Jean-Philippe Polizzi ,  Andre Rouzaud

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/0058 ,  B81B7/0038 ,  B81B7/0077 ,  B81B2201/0228 ,  B81B2207/096 ,  B81C1/00285 ,  B81C1/00301 ,  B81C1/00682 ,  B81C2201/053 ,  B81C2203/0136 ,  B81C2203/0163 ,  H01L2224/16145 ,  H01L2224/16225

    Abstract: A microdevice encapsulation structure arranged in at least one cavity formed between a substrate and a cap rigidly attached to the substrate is provided, the cap including one layer of a first material, one face of which forms an inner wall of the cavity, and mechanical reinforcement portions rigidly attached at least to and partly covering said face, having gas absorption and/or adsorption properties, in which the Young's modulus of a second material of the mechanical reinforcement portions is higher than that of the first material, wherein each of said portions includes at least one first layer of the second material, and at least one second layer of a third metallic getter material such that the first layer of the second material is arranged between the layer of the first material and the second layer of the third material and/or is covered by the second layer of the third material.

    Abstract translation: 提供了一种微型装置封装结构，其设置在形成在基板和刚性地附接到基板的盖之间的至少一个空腔中，所述盖包括一层第一材料，其一个面形成所述空腔的内壁，并且机械加强 至少部分地覆盖所述表面的部分，具有气体吸收和/或吸附性能，其中机械加强部分的第二材料的杨氏模量高于第一材料的杨氏模量，其中每个部分包括 第二材料的至少一个第一层和第三金属吸气剂材料的至少一个第二层，使得第二材料的第一层布置在第一材料的层和第三材料的第二层之间和/ 或被第三材料的第二层覆盖。

    Release chemical protection for integrated complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) devices
    17.
    发明授权
    Release chemical protection for integrated complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) devices 有权
    释放用于集成的互补金属氧化物半导体（CMOS）和微机电（MEMS）器件的化学保护

    公开(公告)号：US09487396B2

    公开(公告)日：2016-11-08

    申请号：US14477451

    申请日：2014-09-04

    Applicant: INVENSENSE, INC.

    Inventor： Michael J. Daneman ,  Fariborz Assaderaghi

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00246 ,  B81B7/0025 ,  B81B7/007 ,  B81B2207/015 ,  B81C1/00531 ,  B81C1/00539 ,  B81C1/00801 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/053 ,  B81C2203/0735

    Abstract: Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.

    Abstract translation: 提供了保护CMOS层免于暴露于释放化学品的系统和方法。 释放化学品用于释放与CMOS晶片集成的微机电（MEMS）器件。 在互补金属氧化物半导体（CMOS）晶片中产生的钝化开口的侧壁暴露了CMOS释放化学品接触时可能损坏的CMOS晶片的电介质层。 在一个方面，为了保护CMOS晶片并防止电介质层的暴露，钝化开口的侧壁可以被抵抗释放化学品的金属阻挡层覆盖。 另外或可选地，可以在CMOS晶片的表面上沉积绝缘阻挡层，以保护钝化层免于暴露于释放化学品。

    Integrated MEMS Device
    18.
    发明申请
    Integrated MEMS Device 有权
    集成MEMS器件

    公开(公告)号：US20160244323A1

    公开(公告)日：2016-08-25

    申请号：US15144896

    申请日：2016-05-03

    Applicant: Asia Pacific Microsystems, Inc.

    Inventor： Jerwei Hsieh

    IPC: B81B7/00

    CPC classification number: B81B7/0038 ,  B81B7/0058 ,  B81B2201/032 ,  B81C1/00238 ,  B81C1/00817 ,  B81C1/00825 ,  B81C2201/053 ,  B81C2201/056 ,  B81C2203/0785

    Abstract: An integrated MEMS device is provided. The integrated MEMS device comprises a circuit chip and a device chip. The circuit chip has a patterned first bonding layer disposed thereon, the bonding layer being composed of a conductive material/materials. The device chip has a first structural layer and a second structural layer, the first structural layer being connected to the second structural layer and the first bonding layer of the circuit chip, and being sandwiched between the second structural layer and the circuit chip. A plurality of hermetic spaces are enclosed by the first structural layer, the second structural layer, the first bonding layer and the circuit chip.

    Abstract translation: 提供集成的MEMS器件。 集成MEMS器件包括电路芯片和器件芯片。 电路芯片具有设置在其上的图案化第一接合层，接合层由导电材料/材料构成。 器件芯片具有第一结构层和第二结构层，第一结构层连接到电路芯片的第二结构层和第一结合层，并夹在第二结构层和电路芯片之间。 第一结构层，第二结构层，第一结合层和电路芯片包围多个封闭空间。

    Method for manufacturing an integrated MEMS device
    19.
    发明授权
    Method for manufacturing an integrated MEMS device 有权
    集成MEMS器件的制造方法

    公开(公告)号：US09359193B2

    公开(公告)日：2016-06-07

    申请号：US14165752

    申请日：2014-01-28

    Applicant: Asia Pacific Microsystems, Inc.

    Inventor： Jerwei Hsieh

    IPC: H01L21/4763 ,  B81C1/00 ,  B81B7/00

    CPC classification number: B81B7/0038 ,  B81B7/0058 ,  B81B2201/032 ,  B81C1/00238 ,  B81C1/00817 ,  B81C1/00825 ,  B81C2201/053 ,  B81C2201/056 ,  B81C2203/0785

    Abstract: An integrated MEMS device and its manufacturing method are provided. In the manufacturing method, the sacrificial layer is used to integrate the MEMS wafer and the circuit wafer. The advantage of the present invention comprises preventing films on the circuit wafer from being damaged during process. By the manufacturing method, a mechanically and thermally stable structure material, for example: monocrystalline silicon and polysilicon, can be used. The integrated MEMS device manufactured can also possess the merit of planar top-surface topography with high fill factor. The manufacturing method is especially suitable for manufacturing MEMS array device.

    Abstract translation: 提供集成的MEMS器件及其制造方法。 在制造方法中，牺牲层用于集成MEMS晶片和电路晶片。 本发明的优点包括防止电路晶片上的膜在加工过程中被损坏。 通过制造方法，可以使用机械和热稳定的结构材料，例如：单晶硅和多晶硅。 制造的集成MEMS器件也可以具有高填充因子的平面顶表面形貌的优点。 该制造方法特别适用于制造MEMS阵列器件。

    Structure and Method for Integrated Microphone
    20.
    发明申请
    Structure and Method for Integrated Microphone 有权
    集成麦克风的结构和方法

    公开(公告)号：US20160157038A1

    公开(公告)日：2016-06-02

    申请号：US15018625

    申请日：2016-02-08

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jung-Huei Peng ,  Chia-Hua Chu ,  Chun-wen Cheng ,  Chin-Yi Cho ,  Li-Min Hung ,  Yao-Te Huang

    IPC: H04R31/00 ,  B81C1/00

    CPC classification number: H04R31/003 ,  B81C1/00158 ,  B81C2201/0125 ,  B81C2201/013 ,  B81C2201/053 ,  B81C2203/036 ,  H04R19/005 ,  H04R19/04 ,  H04R31/006 ,  H04R2201/003 ,  H04R2307/027

    Abstract: The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.

    Abstract translation: 本公开提供了集成麦克风结构的一个实施例。 集成麦克风结构包括图案化为第一板的第一硅衬底。 形成在第一硅衬底的一侧上的氧化硅层。 第二硅衬底通过氧化硅层与第一衬底结合，使得氧化硅层夹在第一和第二硅衬底之间。 一个膜片，其固定在氧化硅层上并且设置在第一和第二硅衬底之间，使得第一板和隔膜被配置成形成电容式麦克风。

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