公开(公告)号：US20160050794A1

公开(公告)日：2016-02-18

申请号：US14779916

申请日：2014-03-26

Applicant: INNOGRATION (SUZHOU) CO., LTD

Inventor： Chu Ming Shih ,  Gordon C. Ma

IPC: H05K7/20 ,  H05K3/00 ,  H05K3/30 ,  H05K7/02

CPC classification number: H05K7/20509 ,  H01L23/3677 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2924/19107 ,  H05K1/0204 ,  H05K3/0044 ,  H05K3/301 ,  H05K7/02 ,  H05K2201/0347 ,  H05K2201/10416 ,  H05K2203/1461

Abstract: An electronic component mounting structure, manufacturing method and an electronic component product are provided. The electronic component mounting structure comprises a printed circuit board, a metal flange, and a plurality of electronic components provided on the metal flange; a groove is provided on the printed circuit board, a metal layer is coated on a wall of the groove, the metal flange is restricted to the metal layer on the wall and is fixed in the groove, the one or more electronic components are connected to each other through a plurality of wires based on a circuit requirement, an input electrode and an output electrode are provided on the printed circuit board in a portion adjacent to the metal flange, and the input electrode and the output electrode are connected to the one or more electronic components mounted on the metal flange through wires respectively.

Abstract translation: 提供电子部件安装结构，制造方法和电子部件产品。 电子部件安装结构包括印刷电路板，金属凸缘和设置在金属凸缘上的多个电子部件; 在印刷电路板上设置有凹槽，金属层涂覆在凹槽的壁上，金属凸缘限于壁上的金属层并固定在凹槽中，一个或多个电子元件连接到 通过基于电路要求的多条导线，输入电极和输出电极设置在与金属凸缘相邻的部分的印刷电路板上，并且输入电极和输出电极连接到一个或 更多的电子元件分别安装在金属法兰上。

公开(公告)号：US20150380391A1

公开(公告)日：2015-12-31

申请号：US14848504

申请日：2015-09-09

Applicant: Zhen Ding Technology Co., Ltd.

Inventor： Yong HA WOO ,  E-Tung CHOU ,  Wen-Lun LO

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H05K1/09 ,  H05K1/11

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/09 ,  H01L2224/08238 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/15738 ,  H01L2924/181 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/0347 ,  H05K2201/0379 ,  H05K2201/09836 ,  H05K2201/10674 ,  H05K2203/0384 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts is larger than that of each of the first conductive posts. A manufacturing method thereof is also provided.

Abstract translation: 封装基板包括电路板，多个第一导电柱和多个第二导电柱。 电路板包括形成在第一基底的第一表面上的第一基底和第一导电图案层。 第一导电柱从第一导电图案层延伸并电连接到第一导电图案层。 第二导电柱从第一导电图案层延伸并与之电连接。 每个第二导电柱的高度大于每个第一导电柱的高度。 还提供了其制造方法。

公开(公告)号：US09226397B2

公开(公告)日：2015-12-29

申请号：US13936420

申请日：2013-07-08

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/16 ,  H05K1/09 ,  H01L23/498 ,  H05K1/02 ,  H05K1/05 ,  H05K1/18 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/09 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/183 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09809 ,  H01L2224/05599

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

Abstract translation: 即使IC芯片处于高频范围，特别是具有频率超过3GHz的IC芯片，也不会出现故障或误差的封装基板。 芯基板30上的导体层34P形成为具有30μm的厚度，层间树脂绝缘层50上的导体电路58形成为具有15μm的厚度。 通过使导体层34P变厚，可以增加导体本身的体积并降低电阻。 此外，通过使用导体层34作为电源层，可以提高向IC芯片供电的能力。

公开(公告)号：US20150282323A1

公开(公告)日：2015-10-01

申请号：US14663921

申请日：2015-03-20

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi Shimizu ,  Wataru Kaneda ,  Akio Rokugawa

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/0222 ,  H05K1/0225 ,  H05K1/0298 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/116 ,  H05K3/26 ,  H05K3/381 ,  H05K3/4673 ,  H05K3/4676 ,  H05K2201/0191 ,  H05K2201/0281 ,  H05K2201/029 ,  H05K2201/0293 ,  H05K2201/0347 ,  H05K2201/068 ,  H05K2201/09227 ,  H05K2201/093 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2203/0514

Abstract: A wiring board includes a first wiring layer formed on one surface of a core layer, a first insulating layer formed on the one surface of the core layer so as to cover the first wiring layer, a via wiring embedded in the first insulating layer, a second wiring layer formed on a first surface of the first insulating layer, and a second insulating layer thinner than the first insulating layer formed on the first surface of the first insulating layer so as to cover the second wiring layer. The first wiring layer comprises a pad and a plane layer provided around the pad. One end surface of the via wiring is exposed from the first surface of the first insulating layer and directly bonded to the second wiring layer. The other end surface of the via wiring is directly bonded to the pad in the first insulating layer.

Abstract translation: 布线基板包括形成在芯层的一个表面上的第一布线层，形成在芯层的一个表面上以覆盖第一布线层的第一绝缘层，嵌入第一绝缘层中的通孔布线， 第二布线层，形成在第一绝缘层的第一表面上，以及比形成在第一绝缘层的第一表面上的第一绝缘层更薄的第二绝缘层，以覆盖第二布线层。 第一布线层包括焊盘和设置在焊盘周围的平面层。 通孔布线的一个端面从第一绝缘层的第一表面露出并直接接合到第二布线层。 通孔布线的另一个端面直接接合到第一绝缘层中的焊盘。

公开(公告)号：US09049791B2

公开(公告)日：2015-06-02

申请号：US13912652

申请日：2013-06-07

Applicant: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

Inventor： Dror Hurwitz ,  Alex Huang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/02 ,  H01L23/00 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15788 ,  H05K1/115 ,  H05K3/0082 ,  H05K3/108 ,  H05K3/282 ,  H05K3/4007 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of attaching a chip to the substrate with an outer layer consisting of via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method consisting of optionally removing an organic varnish, positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and applying heat to melt the solder bumps and to wet the ends of the vias with solder.

Abstract translation: 一种将芯片附着到具有外部层的方法，所述外层由嵌入在电介质如焊料掩模中的通孔柱构成，通孔的端部与所述电介质齐平，所述方法包括任选地除去有机清漆，将芯片定位 具有以与通孔支柱的暴露端接触的焊料凸块端接的腿，并施加热量以熔化焊料凸块并用焊料润湿通孔的端部。

公开(公告)号：US20150083480A1

公开(公告)日：2015-03-26

申请号：US14143536

申请日：2013-12-30

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Seon Hee MOON ,  Seung Wook Park ,  Chang Bae Lee

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/42

CPC classification number: H05K1/116 ,  H05K1/115 ,  H05K3/108 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0347 ,  H05K2201/0959 ,  Y10T29/49165

Abstract: Disclosed herein are an interposer board and a method of manufacturing the same. According to a preferred embodiment of the present invention, the interposer substrate may include: a base substrate; a circuit pattern formed on the base substrate; and a through via formed to penetrate through the base substrate and have a height lower than that of the circuit pattern.

Abstract translation: 这里公开了一种插入板及其制造方法。 根据本发明的优选实施例，插入器基板可以包括：基底; 形成在基底基板上的电路图案; 以及形成为穿过基底基板并且具有低于电路图案的高度的通孔。

公开(公告)号：US20140363927A1

公开(公告)日：2014-12-11

申请号：US13912652

申请日：2013-06-07

Applicant: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co., Ltd.

Inventor： Dror Hurwitz ,  Alex Huang

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H01L23/00

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15788 ,  H05K1/115 ,  H05K3/0082 ,  H05K3/108 ,  H05K3/282 ,  H05K3/4007 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

Abstract translation: 一种将芯片附着到具有外层的方法，外层包括嵌入电介质如焊料掩模中的通孔，通孔的端部与所述电介质齐平，所述方法包括以下步骤：（o）任选地除去有机清漆 ，（p）将具有用焊料凸块端接的腿的芯片定位成与通孔柱的暴露端接触，和（q）施加热量以熔化焊料凸块并用焊料润湿通孔的端部。

公开(公告)号：US20140104227A1

公开(公告)日：2014-04-17

申请号：US13757560

申请日：2013-02-01

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Tae Hoon Kim ,  Seung Min Lee ,  Youn Soo Kim ,  Ho Joon Park ,  Jae Chan Park

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F2203/04103 ,  H05K3/02 ,  H05K3/246 ,  H05K2201/0108 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/0347 ,  H05K2203/0514 ,  H05K2203/0723

Abstract: Disclosed herein are a touch panel and a method for manufacturing the same, the touch panel including: a transparent substrate; a photosensitive ink layer patterned on the transparent substrate and having electric conductivity; and electrode patterns formed at corresponding positions on the patterned photosensitive ink layer, and the method including: preparing a transparent substrate; coating a photosensitive ink having electric conductivity on the transparent substrate to form a photosensitive ink layer; patterning the photosensitive ink layer; and forming electrode patterns on the patterned photosensitive ink layer.

Abstract translation: 这里公开了触摸面板及其制造方法，该触摸面板包括：透明基板; 在透明基板上图案化并具有导电性的感光油墨层; 以及形成在所述图案化感光油墨层上的对应位置处的电极图案，并且所述方法包括：准备透明基板; 在所述透明基板上涂布具有导电性的感光油墨，以形成感光油墨层; 图案化感光油墨层; 以及在图案化感光油墨层上形成电极图案。

公开(公告)号：US08674236B2

公开(公告)日：2014-03-18

申请号：US13368840

申请日：2012-02-08

Applicant: Kazunaga Higo ,  Hidemasa Igarashi ,  Masatsune Arakawa ,  Erina Yamada ,  Kenji Suzuki ,  Tomohito Ando ,  Hironori Sato ,  Takuya Torii

Inventor： Kazunaga Higo ,  Hidemasa Igarashi ,  Masatsune Arakawa ,  Erina Yamada ,  Kenji Suzuki ,  Tomohito Ando ,  Hironori Sato ,  Takuya Torii

IPC: H05K1/11 ,  H05K3/02

CPC classification number: H05K1/0242 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/389 ,  H05K3/4644 ,  H05K2201/0347 ,  H05K2201/098 ,  H01L2924/00

Abstract: A wiring substrate is configured such that each of laminate portions provided above and below a substrate core includes insulating layers and conductor layers stacked alternately. Of the conductor layers of the laminate portions, signal line layers are treated with a silane coupling treatment, which is a surface modification treatment, so that each signal line comprises a flat surface. A roughening treatment is performed on the remaining conductor layers of the laminate portions such that the surfaces of these layers are roughened. This structure provides an advantage when high-frequency signals are transmitted through the signal line layers. That is, when each signal line comprises a flat surface, an increase in conductor loss due to the skin effect can be prevented. In addition, by means of chemical bonding attained through the silane coupling treatment, the reliability of adhesion between the signal line layers and the insulating layer is sufficiently attained.

Abstract translation: 布线基板被构造成使得设置在基板芯的上方和下方的每个层叠部分包括交替堆叠的绝缘层和导体层。 在层压体部分的导体层中，用作为表面改性处理的硅烷偶联处理来处理信号线层，使得每个信号线包括平坦表面。 对层压体部分的剩余导体层进行粗糙化处理，使得这些层的表面变粗糙。 当高频信号通过信号线层传输时，这种结构提供了一个优点。 也就是说，当每个信号线包括平坦表面时，可以防止由于皮肤效应引起的导体损耗的增加。 此外，通过通过硅烷偶联处理获得的化学键合，充分获得信号线层与绝缘层之间的粘合的可靠性。

公开(公告)号：US08664536B2

公开(公告)日：2014-03-04

申请号：US13153590

申请日：2011-06-06

Applicant: Masahiro Sunohara ,  Shigeaki Suganuma

Inventor： Masahiro Sunohara ,  Shigeaki Suganuma

IPC: H05K1/09

CPC classification number: H01L23/49822 ,  H01L23/147 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/388 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/10378 ,  H01L2924/00

Abstract: A wiring substrate includes a wiring layer made of copper, an electrode layer made of copper, and an insulating layer arranged adjacent to the electrode layer. The wiring layer is stacked on the electrode layer and the insulating layer. The insulating layer and the wiring layer are stacked with an adhesive layer interposed between the insulating layer and the wiring layer. The electrode layer and the wiring layer are stacked with a copper alloy layer formed adjacent to the adhesive layer and interposed between the electrode layer and the wiring layer.

Abstract translation: 布线基板包括由铜制成的布线层，由铜制成的电极层和与电极层相邻布置的绝缘层。 布线层堆叠在电极层和绝缘层上。 绝缘层和布线层被叠置在介于绝缘层和布线层之间的粘合剂层。 电极层和布线层与形成在粘合剂层附近的铜合金层层叠，插入在电极层和布线层之间。