中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

198 records (took 0.022 seconds)

    Stack-type semiconductor package sockets and stack-type semiconductor package test systems
    11.
    发明申请
    Stack-type semiconductor package sockets and stack-type semiconductor package test systems 有权

    公开(公告)号：US20080094086A1

    公开(公告)日：2008-04-24

    申请号：US11976128

    申请日：2007-10-22

    Applicant: Woo-Seop Kim

    Inventor： Woo-Seop Kim

    IPC: G01R31/02 ,  H01L23/48

    CPC classification number: G01R31/31905 ,  G01R1/0483 ,  G01R31/318505 ,  H01L2224/16225 ,  H01L2224/73253 ,  H05K1/141 ,  H05K1/145 ,  H05K2201/045 ,  H05K2201/10734

    Abstract: A stack-type semiconductor package socket may include: a first package connection portion for connection with leads of a lowermost package of a stack-type semiconductor package; a second package connection portion for connection between pads of an odd-numbered package and leads of an even-numbered package, wherein the odd-numbered package and the even-numbered package are adjacent to each other; a lower case for fixing the first package connection portion; and an upper case for fixing the second package connection portion. A stack-type semiconductor package test system may include: a stack-type semiconductor package socket that includes first and second package connection portions; a printed circuit board electrically connected to leads of the lowermost package through the first package connection portion; and a test controller for receiving, outputting, or receiving and outputting signals from, to, or from and to the stack-type semiconductor package through the PCB and the stack-type semiconductor package socket.

    Disk unit-integrated display and disk unit-integrated television
    12.
    发明申请
    Disk unit-integrated display and disk unit-integrated television 失效
    磁盘单元集成显示器和磁盘单元集成电视

    公开(公告)号：US20070147796A1

    公开(公告)日：2007-06-28

    申请号：US11642863

    申请日：2006-12-21

    Applicant: Tomokazu Sugamura ,  Masuo Ogawa

    Inventor： Tomokazu Sugamura ,  Masuo Ogawa

    IPC: H04N5/00

    CPC classification number: H04N5/64 ,  B82Y20/00 ,  G11B31/00 ,  G11B33/10 ,  G11B33/12 ,  H04N21/42646 ,  H05K1/14 ,  H05K1/141 ,  H05K1/182 ,  H05K3/0052 ,  H05K3/366 ,  H05K2201/045 ,  H05K2201/048

    Abstract: A disk unit-integrated display capable of increase in conveyance efficiency and reduce in conveyance cost of a disk unit, a holding member and a first circuit board unitized with each other can be obtained. This disk unit-integrated display includes the disk unit having a drive portion, the holding member for supporting the disk unit, the first circuit board arranged between the disk unit and the holding member and having an opening at a position corresponding to the drive portion of the disk unit.

    Abstract translation: 可以获得能够提高输送效率并降低盘单元，保持构件和彼此组合的第一电路板的输送成本的盘单元集成显示器。 该盘单元集成显示器包括具有驱动部分的盘单元，用于支撑盘单元的保持构件，布置在盘单元和保持构件之间的第一电路板，并且在与驱动部分的驱动部分相对应的位置处具有开口 磁盘单元。

    Memory module, memory extension memory module, memory module system, and method for manufacturing a memory module
    13.
    发明申请
    Memory module, memory extension memory module, memory module system, and method for manufacturing a memory module 有权
    存储器模块，存储器扩展存储器模块，存储器模块系统以及用于制造存储器模块的方法

    公开(公告)号：US20070015381A1

    公开(公告)日：2007-01-18

    申请号：US11481676

    申请日：2006-07-06

    Applicant: Simon Muff ,  Siva Raghuram

    Inventor： Simon Muff ,  Siva Raghuram

    IPC: H01R12/00

    CPC classification number: G11C5/04 ,  H05K1/144 ,  H05K3/366 ,  H05K2201/045 ,  H05K2201/10189 ,  H05K2203/1572

    Abstract: A memory extension memory module, a memory module system, and a memory module is disclosed. The memory module including at least one memory device and a connector for connecting the memory module to a computer system, wherein the memory module additionally includes a surface-mounted connector for connecting a memory extension memory module to the memory module. Furthermore, a method for manufacturing a memory module is disclosed. The memory module including at least one memory device and at least one connector for connecting a memory extension memory module to the memory module, wherein the at least one memory device and the at least one connector are connected to the memory module in a single manufacturing process.

    Abstract translation: 公开了一种存储器扩展存储器模块，存储器模块系统和存储器模块。 所述存储器模块包括至少一个存储器件和用于将所述存储器模块连接到计算机系统的连接器，其中所述存储器模块还包括用于将存储器扩展存储器模块连接到所述存储器模块的表面安装连接器。 此外，公开了一种用于制造存储器模块的方法。 所述存储器模块包括至少一个存储器设备和用于将存储器扩展存储器模块连接到所述存储器模块的至少一个连接器，其中所述至少一个存储器设备和所述至少一个连接器在单个制造过程中连接到所述存储器模块 。

    Electromagnetic bus coupling having an electromagnetic coupling interposer
    16.
    发明授权
    Electromagnetic bus coupling having an electromagnetic coupling interposer 失效
    具有电磁耦合插入器的电磁总线耦合器

    公开(公告)号：US07068120B2

    公开(公告)日：2006-06-27

    申请号：US10183614

    申请日：2002-06-25

    Applicant: Yinan Wu ,  Tao Liang ,  John R. Benham

    Inventor： Yinan Wu ,  Tao Liang ,  John R. Benham

    IPC: H01P5/02 ,  H01P5/18

    CPC classification number: H01R12/526 ,  H05K1/0239 ,  H05K1/14 ,  H05K1/141 ,  H05K7/1458 ,  H05K2201/044 ,  H05K2201/045

    Abstract: An assembly (for example, an assembly in the form of an interposer that is distinct from a motherboard and from the devices that communicate with the motherboard) includes electromagnetic couplings. Each of the electromagnetic couplings couples signals being communicated between a device and a bus. Each of the electromagnetic couplings is connected to (a) an associated bus connector to provide connections of the couplings to the bus, and (b) an associated device connector to provide connections of the couplings to the device.

    Abstract translation: 组件（例如，与主板和与主板通信的设备不同的插入件形式的组件）包括电磁耦合。 每个电磁耦合耦合在设备和总线之间传送的信号。 每个电磁耦合器连接到（a）相关联的总线连接器以提供耦合到总线的连接，以及（b）相关联的设备连接器，以提供耦合到设备的连接。

    Multi-chips module assembly package
    17.
    发明授权
    Multi-chips module assembly package 有权
    多芯片模块组装包装

    公开(公告)号：US07015571B2

    公开(公告)日：2006-03-21

    申请号：US10704793

    申请日：2003-11-12

    Applicant: Chih-Huang Chang ,  Shih-Chang Lee

    Inventor： Chih-Huang Chang ,  Shih-Chang Lee

    IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H05K1/144 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/429 ,  H05K2201/045 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/10378

    Abstract: A multi-chips module assembly package mainly comprises a first package, a second package and an intermediate substrate. The intermediate substrate includes an opening, at least a via and a plurality of circuit layers, wherein the second package is accommodated in the opening. The via has an inner wall, and a plurality of separated electrically conductive layers, which is formed on the inner wall and connected with the corresponding circuit layers. The first package electrically connects with the second package through the intermediate substrate, and the intermediate substrate is interposed between the first package and the second package. At least an insulator is formed in the via, and the separated electrically conductive layers are separated from each other. After the intermediate substrate is interposed between the first package and the second package, there will be not enough space between the intermediate substrate, the first package and the second package for disposing conductive devices therein. Therefore, the first package will be electrically connected to the second package through the separated electrically conductive layers of the intermediate substrate for providing more conductive devices disposed and interposed between the intermediate substrate, the first package and the second package.

    Abstract translation: 多芯片模块组装封装主要包括第一封装，第二封装和中间基板。 中间基板包括开口，至少通孔和多个电路层，其中第二封装容纳在开口中。 通孔具有内壁和多个分离的导电层，其形成在内壁上并与相应的电路层连接。 第一包装通过中间基板与第二包装电连接，并且中间基板插入在第一包装和第二包装之间。 至少在通孔中形成绝缘体，并且分离的导电层彼此分离。 在中间基板插入在第一封装和第二封装之间之后，中间基板，第一封装和第二封装之间将没有足够的空间用于在其中设置导电器件。 因此，第一封装将通过中间衬底的分离的导电层电连接到第二封装，用于提供设置和介于中间衬底，第一封装和第二封装之间的更多导电器件。

    Hierarchical module
    19.
    发明申请
    Hierarchical module 失效
    分层模块

    公开(公告)号：US20050270875A1

    公开(公告)日：2005-12-08

    申请号：US11145009

    申请日：2005-06-06

    Applicant: Takanori Saeki

    Inventor： Takanori Saeki

    IPC: G06F13/16 ,  G06F12/00 ,  G11C5/06 ,  G11C7/00 ,  H05K1/14 ,  H05K3/36

    CPC classification number: G11C5/066 ,  G06F13/1684 ,  G11C5/04 ,  H05K1/14 ,  H05K1/141 ,  H05K3/366 ,  H05K2201/045 ,  H05K2201/10159 ,  Y02D10/14

    Abstract: There is provided a memory module that facilitates meeting the needs of high-speed performance and large capacity. It comprises first module substrates (10 through 108), each with multiple DRAM devices (11), and a second module substrate whereon the first modules (10 through 108) are mounted, signal line groups connected to the multiple first modules respectively are provided in parallel, and a controller LSI (50), connected to the multiple first modules respectively via the signal line groups provided in parallel, that converts the signal lines into fewer signal lines than the total number of the signal line groups and outputs the result is provided, and the second module substrate (20) is mounted on a motherboard (40).

    Abstract translation: 提供了一个可以满足高速性能和大容量需求的内存模块。 它包括第一模块衬底（10至108），每个具有多个DRAM器件（11），以及安装有第一模块（10至108）的第二模块衬底，分别连接到多个第一模块的信号线组 并联的控制器LSI（50），分别经由并联设置的信号线组连接到多个第一模块，将信号线转换成比信号线组的总数少的信号线，并输出结果 ，并且第二模块基板（20）安装在母板（40）上。

    Converter device
    20.
    发明授权
    Converter device 有权
    转换器设备

    公开(公告)号：US06914786B1

    公开(公告)日：2005-07-05

    申请号：US09881151

    申请日：2001-06-14

    Applicant: Erik Paulsen ,  William Page ,  Erich S. Otto

    Inventor： Erik Paulsen ,  William Page ,  Erich S. Otto

    IPC: H01L23/498 ,  H01L23/538 ,  H01R12/16 ,  H05K1/14 ,  H05K3/34

    CPC classification number: H05K1/141 ,  H01L23/49833 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/144 ,  H05K3/3436 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/10734

    Abstract: The present invention is directed to a converter device. In a first aspect of the present invention, a converter device includes a board having a first side and a second side. The first side includes a first set of contacts suitable for electrically contacting an integrated circuit having a first configuration. The second side includes a second set of contacts suitable for electrically contacting a circuit board having a second configuration. The second set of contacts is communicatively coupled to the first set of contacts.

    Abstract translation: 本发明涉及一种转换器装置。 在本发明的第一方面，一种转换器装置包括具有第一侧和第二侧的板。 第一侧包括适于电接触具有第一构造的集成电路的第一组触点。 第二侧包括适于电接触具有第二构造的电路板的第二组触点。 第二组触点通信地耦合到第一组触点。

Patent Agency Ranking