公开(公告)号：US20150223323A1

公开(公告)日：2015-08-06

申请号：US14173106

申请日：2014-02-05

Applicant: Colin Patrick O'Flynn

Inventor： Colin Patrick O'Flynn

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0253 ,  H05K1/111 ,  H05K2201/094 ,  H05K2201/09409 ,  H05K2201/09427 ,  Y02P70/611

Abstract: A PCB footprint consisting of a plurality of pads, positioned such that many different electronic components can be mounted which would otherwise require a custom circuit board. One or more of the leads can be connected via a low-impedance path to a ground plane, making a suitable platform for prototyping high-frequency designs.

Abstract translation: 由多个焊盘组成的PCB封装，定位成使得可以安装许多不同的电子部件，否则其将需要定制的电路板。 一个或多个引线可以通过低阻抗路径连接到接地平面，为高频设计的原型设计提供了一个合适的平台。

公开(公告)号：US20140345920A1

公开(公告)日：2014-11-27

申请号：US14273657

申请日：2014-05-09

Applicant: Nitto Denko Corporation

Inventor： Terukazu IHARA ,  Naohiro TERADA

IPC: H05K1/09 ,  H05K3/34

CPC classification number: H05K3/3405 ,  G11B5/4853 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2203/046 ,  Y10T29/49147

Abstract: Heat-assisted wiring traces and a conductive support substrate are respectively formed on first and second surfaces of an insulating layer. Further, connection terminals electrically insulated from the support substrate and electrically respectively connected to the heat-assisted wiring traces are formed on the second surface of the insulating layer. Each connection terminal has an element connection portion, a pattern connection portion and a spread blocking portion. When a circuit element is connected to the element connection portion of the connection terminal by solder, spreading of a molten solder applied to the element connection portion to the pattern connection portion is blocked by the spread blocking portion.

Abstract translation: 分别在绝缘层的第一和第二表面上形成热辅助布线和导电支撑基板。 此外，在绝缘层的第二表面上形成与支撑基板电绝缘并电连接到热辅助布线的连接端子。 每个连接端子具有元件连接部分，图案连接部分和展开阻挡部分。 当通过焊料将电路元件连接到连接端子的元件连接部分时，施加到元件连接部分的熔融焊料向图案连接部分的扩散被扩展阻挡部分阻挡。

公开(公告)号：US08607446B2

公开(公告)日：2013-12-17

申请号：US13182364

申请日：2011-07-13

Applicant: Kenji Fukuda

Inventor： Kenji Fukuda

IPC: H01R9/00 ,  H05K3/00

CPC classification number: B23K1/0016 ,  B23K2101/40 ,  H01L24/17 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/09418 ,  H05K2201/09427 ,  H05K2203/0465 ,  Y02P70/613 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49204 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of manufacturing an electronic component, which includes arranging a plurality of first electrode pads on a first substrate, and a plurality of second electrode pads on a second substrate, so that the first and second electrode pads correspond to each other. The method further includes forming a plurality of solder bumps on the second electrode pads and putting the first substrate over the second substrate. The first and second substrates are shifted in parallel to each other, in a horizontal direction, while the solder bumps are melting, so that the solder bumps are stretched in a slant direction to cause the solder bumps to be solidified into hourglass-shapes.

Abstract translation: 一种制造电子部件的方法，其包括在第一基板上布置多个第一电极焊盘，在第二基板上布置多个第二电极焊盘，使得第一和第二电极焊盘彼此对应。 该方法还包括在第二电极焊盘上形成多个焊料凸块并将第一衬底放置在第二衬底上。 第一基板和第二基板在水平方向上彼此平行地移动，同时焊料凸点熔化，使得焊料凸块沿倾斜方向拉伸以使焊料凸块固化成沙漏形状。

公开(公告)号：US20130313007A1

公开(公告)日：2013-11-28

申请号：US13901398

申请日：2013-05-23

Applicant: Massachusetts Institute of Technology

Inventor： Dmitry Tolpin ,  James H. Kelly ,  Roger M. Maurais

IPC: H05K1/11 ,  H05K3/30

CPC classification number: H05K3/301 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/351 ,  H01L2924/381 ,  H05K1/111 ,  H05K1/18 ,  H05K1/181 ,  H05K3/30 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/09418 ,  H05K2201/09427 ,  H05K2201/10242 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49133 ,  H01L2924/00

Abstract: Reliability is improved for the mechanical electrical connection formed between a grid array device, such as a pin grid array device (PGA) or a column grid array device (CGA), and a substrate such as a printed circuit board (PCB). Between adjacent PCB pads, a spacing pattern increases toward the periphery of the CGA, creating a misalignment between pads and columns. As part of the assembly method, columns align with the pads, resulting in column tilt that increases from the center to the periphery of the CGA. An advantage of this tilt is that it reduces the amount of contractions and expansions of columns during thermal cycling, thereby increasing the projected life of CGA. Another advantage of the method is that it reduces shear stress, further increasing the projected life of the CGA.

Abstract translation: 对于诸如针阵列阵列器件（PGA）或列格栅阵列器件（CGA）的栅格阵列器件和诸如印刷电路板（PCB）的衬底之间形成的机械电连接，可靠性得到改善。 在相邻的PCB焊盘之间，间隔图案朝向CGA的周边增加，导致焊盘和柱之间的未对准。 作为组装方法的一部分，列与焊盘对准，导致从CGA的中心到外围增加的列倾斜。 这种倾斜的一个优点是在热循环期间减少了柱的收缩量和膨胀量，从而增加了CGA的预计使用寿命。 该方法的另一个优点是降低了剪切应力，进一步提高了CGA的寿命。

公开(公告)号：US20130128480A1

公开(公告)日：2013-05-23

申请号：US13680810

申请日：2012-11-19

Applicant: Robert Bosch GmbH

Inventor： Alexander Bareiss

IPC: H05K7/06

CPC classification number: H05K7/06 ,  H05K1/182 ,  H05K1/184 ,  H05K3/182 ,  H05K3/3442 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09427 ,  H05K2201/09981 ,  H05K2201/10636 ,  H05K2201/2036 ,  H05K2203/048 ,  Y02P70/611 ,  Y02P70/613

Abstract: A circuit arrangement includes at least one electronic and/or electrical component and a carrier. The at least one electronic and/or electrical component is conductively connected to the carrier by at least one solder layer while forming an air space between the electronic and/or electrical component and the carrier. At least one three-dimensional mounting structure is integrated in the carrier and the at least one electronic and/or electrical component is arranged axially between at least two contact regions of the mounting structure.

Abstract translation: 电路装置包括至少一个电子和/或电气部件和载体。 所述至少一个电子和/或电气部件通过至少一个焊料层导电地连接到所述载体，同时在所述电子部件和/或电气部件与所述载体之间形成空气空间。 至少一个三维安装结构集成在载体中，并且至少一个电子和/或电气部件被轴向地布置在安装结构的至少两个接触区域之间。

公开(公告)号：US08446007B2

公开(公告)日：2013-05-21

申请号：US12784327

申请日：2010-05-20

Applicant: Hung-Jui Kuo ,  Chung-Shi Liu ,  Chen-Hua Yu

Inventor： Hung-Jui Kuo ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/52

CPC classification number: H01L22/12 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/06131 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/14104 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/0001 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09427 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit structure includes a work piece selected from the group consisting of a semiconductor chip and a package substrate. The work piece includes a plurality of under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of metal bumps, with each of the plurality of metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps.

Abstract translation: 集成电路结构包括从由半导体芯片和封装基板构成的组中选择的工件。 工件包括分布在工件的主表面上的多个凸块下金属（UBM）; 以及多个金属凸块，其中所述多个金属凸块中的每一个直接在所述多个UBM中的一个上，并且电连接到所述多个UBM中的一个。 多个UBM和多个金属凸块被分配有覆盖偏移，多个UBM中的至少一些与多个金属凸块中相应的上覆的UBM不对准。

公开(公告)号：US20120305305A1

公开(公告)日：2012-12-06

申请号：US13151145

申请日：2011-06-01

Applicant: Suresh Upadhyayula ,  Naveen Kini

Inventor： Suresh Upadhyayula ,  Naveen Kini

IPC: H05K1/11 ,  H01L23/488

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/15311 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09427 ,  H01L2924/00012

Abstract: A system of micro balls is disclosed for coupling an electronic component to a printed circuit board. The micro balls have a small diameter, and each contact pad may include an array of two or more micro balls. An example of a micro ball may include a polymer core, surrounded by a copper layer, which is in turn surrounded by a layer of solder.

Abstract translation: 公开了一种用于将电子部件耦合到印刷电路板的微球系统。 微球具有小直径，并且每个接触垫可以包括两个或更多个微球的阵列。 微球的例子可以包括由铜层包围的聚合物芯，该铜层又被一层焊料包围。

公开(公告)号：US08318537B2

公开(公告)日：2012-11-27

申请号：US12757889

申请日：2010-04-09

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L21/00 ,  H01L29/40

CPC classification number: H01L23/49838 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.

Abstract translation: 通过将互连凸块配合到引线或迹线上的窄互连焊盘而不是捕获板上，来制造衬底上的管芯的倒装芯片互连。 窄互连焊盘的宽度小于要连接的裸片上的凸块的基底直径。 此外，倒装芯片封装包括具有附着到有源表面中的互连焊盘的焊料凸块的芯片，以及在芯片附着表面中的导电迹线上具有窄互连焊盘的衬底，其中凸块配合到 痕迹

公开(公告)号：US20120241946A9

公开(公告)日：2012-09-27

申请号：US12961027

申请日：2010-12-06

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/3205

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0901 ,  H01L2224/1134 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81136 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.

Abstract translation: 半导体器件具有在半导体管芯的表面上的接触焊盘上形成有多个凸点的半导体管芯。 凸块可以具有可熔部分和非易熔部分。 在衬底上形成多个导电迹线，其互连位置的宽度大于凸块和接触焊盘之间的接触界面的20％且小于80％的宽度。 这些凸块被结合到互连部位，使得凸块覆盖互连部位的顶表面和侧表面。 围绕半导体管芯和衬底之间的凸块沉积密封剂。 导电迹线具有通过可以放置在衬底上的相邻导电迹线之间的最小间隔确定的间距，并且互连部位的宽度提供等于导电迹线的间距的布线密度。

公开(公告)号：US20120211880A9

公开(公告)日：2012-08-23

申请号：US12757889

申请日：2010-04-09

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L23/49838 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.

Abstract translation: 通过将互连凸块配合到引线或迹线上的窄互连焊盘而不是捕获板上，来制造衬底上的管芯的倒装芯片互连。 窄互连焊盘的宽度小于要连接的裸片上的凸块的基底直径。 此外，倒装芯片封装包括具有附着到有源表面中的互连焊盘的焊料凸块的芯片，以及在芯片附着表面中的导电迹线上具有窄互连焊盘的衬底，其中凸块配合到 痕迹