公开(公告)号：US20100123993A1

公开(公告)日：2010-05-20

申请号：US12370394

申请日：2009-02-12

Applicant: Herzel Laor

Inventor： Herzel Laor

IPC: H01G4/005 ,  H01M4/00 ,  B05D5/12 ,  B01J35/10

CPC classification number: B01J37/0238 ,  B01J23/40 ,  H01G4/33 ,  H01G9/0032 ,  H01G9/07 ,  H01G9/15 ,  H01M4/0428 ,  H01M4/64 ,  H05K1/092 ,  H05K1/162 ,  H05K2201/0116 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2203/1131 ,  Y10T29/49002

Abstract: The present disclosure relates generally to the field of sequential surface chemistry. More specifically, it relates to products and methods for manufacturing products using Atomic Layer Deposition (“ALD”) to depose one or more materials onto a surface. ALD is an emerging variant of Chemical Vapor Deposition (“CVD”) technology with capability for high-quality film deposition at low pressures and temperatures, which may produce defect-free films, on a macroscopic scale, at any given thickness. The present disclosure includes, in varying embodiments, methods of manufacturing microelectronic assemblies and components such as battery electrodes, capacitors, resistors, catalyzers and PCB assemblies by ALD, and the products manufactured by those methods.

Abstract translation: 本公开一般涉及顺序表面化学领域。 更具体地说，本发明涉及使用原子层沉积（“ALD”）制造产品以将一种或多种材料沉积到表面上的产品和方法。 ALD是化学气相沉积（“CVD”）技术的新兴变体，具有在低压和高温下高质量薄膜沉积的能力，可在任何给定厚度的宏观尺度上产生无缺陷的薄膜。 本公开在不同的实施例中包括通过ALD制造微电子组件和诸如电池电极，电容器，电阻器，催化剂和PCB组件的组件的方法，以及由这些方法制造的产品。

公开(公告)号：US07690109B2

公开(公告)日：2010-04-06

申请号：US11410984

申请日：2006-04-26

Applicant: Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

Inventor： Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

IPC: H01K3/10

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/0366 ,  H05K1/162 ,  H05K3/0041 ,  H05K3/0044 ,  H05K3/388 ,  H05K3/4061 ,  H05K3/4069 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/09763 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/1338 ,  H05K2203/1581 ,  Y10T29/43 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

Abstract translation: 在层叠在所述芯板的一个表面上的芯板，布线层和电绝缘层的多层布线基板中，所述芯板的XY方向的热膨胀系数在2〜20ppm的范围内 所述芯板的核心部件是选自硅，陶瓷，玻璃，玻璃 - 环氧复合材料和金属的核心部件，所述芯板设置有多个在正面和背面之间导电的通孔 通过导电材料，并且在所述芯板的一个表面上设置电容器，其中所述电容器包括在所述通孔中作为导电材料的上电极和设置成经由电介质层面对所述上电极的下电极 。

公开(公告)号：US20100044089A1

公开(公告)日：2010-02-25

申请号：US12529378

申请日：2008-02-28

Applicant: Akinobu Shibuya ,  Yasuhiro Ishii ,  Toru Mori ,  Koichi Takemura

Inventor： Akinobu Shibuya ,  Yasuhiro Ishii ,  Toru Mori ,  Koichi Takemura

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L27/016 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K3/4614 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10378 ,  H05K2203/061 ,  Y10T29/4913 ,  H01L2924/00014

Abstract: An interposer integrated with capacitors (100) includes a plug substrate (10) in which via-plugs (12) is formed, and a capacitor substrate (20) in which capacitors are formed. The capacitor substrate (20) includes a substrate body (21), capacitors (22) formed on the main surface of the substrate body, a cover insulating film (25) that covers the capacitors, a terminal electrodes (26) connected to the electrodes of the capacitor and formed on the cover insulating film, electrode pads (24) formed on the rear surface of the substrate body, and via-plugs 23 connecting together the terminal electrodes and electrode pads. The plug substrate (10) includes a substrate body (11), and electrode pads (13) formed on the main surface of the substrate body corresponding to the terminal electrodes of the capacitor substrate, and via-plugs (12) penetrating the substrate body and connected to the electrode pads.

Abstract translation: 与电容器（100）集成的插入器包括其中形成有通孔（12）的插头基板（10）和形成有电容器的电容器基板（20）。 电容器基板（20）包括基板主体（21），形成在基板主体的主表面上的电容器（22），覆盖电容器的覆盖绝缘膜（25），与电极连接的端子电极 的电容器，形成在覆盖绝缘膜上，形成在基板主体的后表面上的电极焊盘（24）以及将端子电极和电极焊盘连接在一起的通孔塞23。 插头基板（10）包括基板主体（11），和形成在基板主体的与主电极基板的端子电极对应的主面上的电极焊盘（13）以及穿过基板体的通孔（12） 并连接到电极焊盘。

公开(公告)号：US20100020473A1

公开(公告)日：2010-01-28

申请号：US12180768

申请日：2008-07-28

Applicant: John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Antony P. Chacko ,  Gregory J. Dunn

Inventor： John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Antony P. Chacko ,  Gregory J. Dunn

IPC: H01G9/15

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G9/042 ,  H01G9/045 ,  H01G9/15 ,  H05K3/429 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09909 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/435

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract translation: 一种用于形成具有电容的叠层的方法和由此形成的层压体。 该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。 在电介质上形成导电层。 处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。 在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。

公开(公告)号：US07609141B2

公开(公告)日：2009-10-27

申请号：US11679061

申请日：2007-02-26

Applicant: Edwin James Harris ,  Timothy Pachla ,  Tushar Vyas

Inventor： Edwin James Harris ,  Timothy Pachla ,  Tushar Vyas

IPC: H01C7/10

CPC classification number: H01C7/12 ,  H01G2/14 ,  H02H9/044 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/167 ,  H05K3/28 ,  H05K2201/0738 ,  H05K2201/09763

Abstract: A first voltage variable material (“VVM”) includes an insulative binder, first conductive particles with a core and a shell held in the insulating binder and second conductive particles without a shell held in the insulating binder; a second VVM includes an insulating binder, first conductive particles with a core and a shell held in the insulating binder, second conductive particles without a shell held in the insulating binder, and semiconductive particles with a core and a shell held in the insulating binder; a third VVM includes only first conductive particles with a core and a shell held in the insulating binder.

Abstract translation: 第一电压可变材料（“VVM”）包括绝缘粘合剂，具有芯和保持在绝缘粘合剂中的壳的第一导电颗粒和没有保持在绝缘粘合剂中的壳的第二导电颗粒; 第二VVM包括绝缘粘合剂，具有芯和保持在绝缘粘合剂中的壳的第一导电颗粒，没有保持在绝缘粘合剂中的壳的第二导电颗粒和保持在绝缘粘合剂中的芯和壳的半导体颗粒; 第三VVM仅包括具有芯和保持在绝缘粘合剂中的壳的第一导电颗粒。

公开(公告)号：US20090242257A1

公开(公告)日：2009-10-01

申请号：US12410699

申请日：2009-03-25

Applicant: Shinichiro KAKEI ,  Kenji HORINO ,  Hitoshi SAITA ,  Yasunobu OIKAWA

Inventor： Shinichiro KAKEI ,  Kenji HORINO ,  Hitoshi SAITA ,  Yasunobu OIKAWA

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K3/382 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2203/033

Abstract: In a dielectric element, the side faces are roughened so that the surface roughness Ra is 15 nm or greater. By this means, the area of contact between a glass epoxy resin substrate and insulating material is increased, adhesion with resin substrates is improved, and strength and reliability can be enhanced when buried between two resin substrates. In the dielectric element, the surface roughness Ra of side surfaces is 5000 nm or less, so that when burying the dielectric element between a glass epoxy resin substrate and insulating material, the occurrence of air bubbles between the surface of the dielectric element and the resin can be prevented.

Abstract translation: 在电介质元件中，侧面粗糙化，使得表面粗糙度Ra为15nm以上。 通过这种方式，玻璃环氧树脂基板和绝缘材料之间的接触面积增加，与树脂基板的粘合性提高，并且当埋在两个树脂基板之间时可以提高强度和可靠性。 在电介质元件中，侧面的表面粗糙度Ra为5000nm以下，因此当在玻璃环氧树脂基板和绝缘材料之间埋入电介质元件时，介电元件表面与树脂之间产生气泡 可以防止。

公开(公告)号：US20090200069A1

公开(公告)日：2009-08-13

申请号：US12419007

申请日：2009-04-06

Applicant: Takashi KARIYA ,  Akira Mochida

Inventor： Takashi KARIYA ,  Akira Mochida

IPC: H05K1/03 ,  H05K1/11 ,  H05K1/16 ,  H05K1/09

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic. With this structure, the static capacitance of the layered capacitor portion 40 can be high, and an adequate decoupling effect is exhibited even under circumstances in which instantaneous potential drops occur readily.

Abstract translation: 多层印刷电路板10包括：安装部分60，其顶表面上安装有电连接到布线图案32的半导体元件; 以及具有由陶瓷形成的高介电常数层43的电容器部分40和夹在高介电常数层43上的第一和第二层电极41和42。第一和第二层电极41和42中的一个连接到 半导体元件的电源线和第一和第二层电极41和42中的另一个连接到接地线。 在这种多层印刷电路板10中，连接在电源线和接地线之间的层状电容器部分40中包括的高介电常数层43由陶瓷形成。 利用这种结构，层状电容器部分40的静态电容可以很高，并且即使在容易发生瞬时电位下降的情况下也可以发挥足够的去耦效应。

公开(公告)号：US07548432B2

公开(公告)日：2009-06-16

申请号：US11089450

申请日：2005-03-24

Applicant: Chee Wai Lu ,  Boon Keng Lok ,  Kai Meng Chua ,  Lai Lai Wai

Inventor： Chee Wai Lu ,  Boon Keng Lok ,  Kai Meng Chua ,  Lai Lai Wai

IPC: H05K1/18

CPC classification number: H01G4/232 ,  H01G4/40 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/185 ,  H05K3/429 ,  H05K2201/09718 ,  H05K2201/09763 ,  H01L2224/0401

Abstract: An embedded capacitor structure comprising a main body; at least one embedded capacitor, having a first electrode, a dielectric layer, and a second electrode, formed in the main body; and at least one via electrical connection formed in the main body; wherein at least one of the first and second electrodes is free from direct electrical connection to the via electrical connections.

Abstract translation: 一种嵌入式电容器结构，包括主体; 至少一个嵌入式电容器，具有形成在主体中的第一电极，电介质层和第二电极; 以及形成在主体中的至少一个通孔电连接; 其中所述第一和第二电极中的至少一个电极没有与所述通孔电连接件的直接电连接。

公开(公告)号：US20090141425A1

公开(公告)日：2009-06-04

申请号：US11949914

申请日：2007-12-04

Applicant: Thomas Eugene Dueber ,  Frank Leonard Schadt, III ,  John D. Summers

Inventor： Thomas Eugene Dueber ,  Frank Leonard Schadt, III ,  John D. Summers

IPC: H05K3/30 ,  C08G73/06 ,  H01G4/12 ,  B05D5/12

CPC classification number: H05K1/162 ,  C08G73/22 ,  C09D11/033 ,  C09D11/102 ,  C09D179/04 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K3/285 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates to compositions and methods for using such compositions to provide protective coatings, particularly of electronic components. Fired-on-foil ceramic capacitors coated with a polybenzoxazole encapsulant which may be embedded in printed wiring boards are disclosed.

Abstract translation: 本公开涉及使用这种组合物来提供保护性涂层，特别是电子部件的组合物和方法。 公开了涂覆有可以嵌入印刷线路板中的聚苯并恶唑密封剂的箔状陶瓷电容器。

公开(公告)号：US07531416B2

公开(公告)日：2009-05-12

申请号：US11313562

申请日：2005-12-21

Applicant: Daniel Irwin Amey, Jr. ,  William J. Borland

Inventor： Daniel Irwin Amey, Jr. ,  William J. Borland

IPC: H01L21/8222

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01G4/33 ,  H01L23/50 ,  H01L23/66 ,  H01L27/013 ,  H01L2924/0002 ,  H01L2924/19103 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/162 ,  H05K2201/09763 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: Thick-film capacitors are formed on ceramic interconnect substrates having high capacitance densities and other desirable electrical and physical properties. The capacitor dielectrics are fired at high temperatures.

Abstract translation: 在具有高电容密度和其它所需电气和物理特性的陶瓷互连基板上形成厚膜电容器。 电容器电介质在高温下烧制。