公开(公告)号：US20170324391A1

公开(公告)日：2017-11-09

申请号：US15336991

申请日：2016-10-28

Applicant: Alpha Networks Inc.

Inventor： Rong- Fa KUO

IPC: H03H7/38

CPC classification number: H03H7/38 ,  H01P5/02 ,  H05K1/0222 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/0979

Abstract: An impedance matching structure is disposed on a circuit board for matching an impedance of a transmission line for transmitting an electronic signal. The structure includes: at least two redundant conducting sections coupled to different points between an input terminal and an output terminal of the transmission line, wherein the redundant conducting sections are apart from one another, and a first terminal of each of the redundant conducting sections is coupled to the transmission line, while a second terminal of each of the redundant conducting sections is apart from the transmission line; and at least one grounded conducting section, each of which corresponds to one of the redundant conducting sections, and surrounds in separation from the corresponding redundant conducting section, wherein each of the at least two redundant conducting sections is disposed in a corresponding plating hole.

公开(公告)号：US20170244145A1

公开(公告)日：2017-08-24

申请号：US15587770

申请日：2017-05-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru KATO

IPC: H01P3/08 ,  H05K1/11 ,  H05K1/02

CPC classification number: H01P3/082 ,  H01P1/20363 ,  H01P3/084 ,  H01P3/085 ,  H05K1/0225 ,  H05K1/0242 ,  H05K1/115 ,  H05K1/147 ,  H05K2201/09618 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/0979

Abstract: A high-frequency signal line includes a dielectric body including a first dielectric layer and one or more other dielectric layers laminated together. A first signal line is provided on a first main surface, which is a main surface located on one side in a direction of lamination, of the first dielectric layer. A second signal line is provided on a second main surface, which is a main surface located on another side in the lamination direction, of the first dielectric layer so as to face the first signal line via the first dielectric layer. The second signal line is electrically connected to the first signal line. A first ground conductor is located on one side in the lamination direction than the first signal line. A second ground conductor is located on another side in the lamination direction than the second signal line.

公开(公告)号：US09699901B2

公开(公告)日：2017-07-04

申请号：US14016398

申请日：2013-09-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Kai Yao ,  Yongfa Zhu ,  Yingpei Huang

IPC: H05K5/00 ,  H05K1/11 ,  H05K1/02 ,  H05K3/40

CPC classification number: H05K1/117 ,  H05K1/0265 ,  H05K1/0298 ,  H05K3/4046 ,  H05K2201/0919 ,  H05K2201/09481 ,  H05K2201/0979 ,  H05K2201/10416

Abstract: A golden finger and a board edge interconnecting device are disclosed. The golden finger includes a printed circuit board (PCB) surface layer and at least one PCB inner layer, where a metal foil of the PCB inner layer is connected to a metal foil of the PCB surface layer through a current-carrying structure, so that a current-carrying channel of the golden finger passes through the PCB surface layer and the PCB inner layer. The board edge interconnecting device includes the foregoing golden finger. In the embodiments, a current-carrying capacity of a PCB in the golden finger is increased without increasing a size and thickness of a copper foil of the PCB in the golden finger, thereby effectively improving the current-carrying capacity of the PCB in the golden finger.

公开(公告)号：US09680195B2

公开(公告)日：2017-06-13

申请号：US14568341

申请日：2014-12-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru Kato

IPC: H01P3/08 ,  H05K1/02 ,  H05K1/14 ,  H01P1/203

CPC classification number: H01P3/082 ,  H01P1/20363 ,  H01P3/084 ,  H01P3/085 ,  H05K1/0225 ,  H05K1/0242 ,  H05K1/115 ,  H05K1/147 ,  H05K2201/09618 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/0979

Abstract: A high-frequency signal line includes a dielectric body including a first dielectric layer and one or more other dielectric layers laminated together. A first signal line is provided on a first main surface, which is a main surface located on one side in a direction of lamination, of the first dielectric layer. A second signal line is provided on a second main surface, which is a main surface located on another side in the lamination direction, of the first dielectric layer so as to face the first signal line via the first dielectric layer. The second signal line is electrically connected to the first signal line. A first ground conductor is located on one side in the lamination direction than the first signal line. A second ground conductor is located on another side in the lamination direction than the second signal line.

公开(公告)号：US09661761B2

公开(公告)日：2017-05-23

申请号：US13965194

申请日：2013-08-13

Applicant: Unimicron Technology Corp.

Inventor： Chun-Ting Lin

IPC: H05K3/46 ,  H05K3/40 ,  H05K3/06 ,  H01L23/00

CPC classification number: H05K3/40 ,  H01L21/67265 ,  H01L21/673 ,  H01L21/67346 ,  H01L21/67763 ,  H01L21/6779 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/12042 ,  H05K1/11 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0979 ,  H05K2203/0369 ,  H05K2203/0376 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00

Abstract: A carrier substrate includes an insulation layer, conductive towers and a circuit structure layer. A diameter of each of the conductive towers is increased gradually from a top surface to a bottom surface, and the conductive towers include first conductive towers and second conductive towers surrounding the first conductive towers. The circuit structure layer is disposed on the insulation layer and includes at least one dielectric layer, at least two circuit layers and first conductive vias. Each of the second conductive towers correspondingly connects to at least two of the first conductive vias, and each of the first conductive towers correspondingly connects to one of the first conductive vias. An interface exists between the first conductive vias and the first and the second conductive towers.

公开(公告)号：US09565775B2

公开(公告)日：2017-02-07

申请号：US14469782

申请日：2014-08-27

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi Shimizu ,  Wataru Kaneda ,  Hiromu Arisaka ,  Akio Rokugawa

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/00 ,  H05K1/18 ,  H05K7/10 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K3/421 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/115 ,  H05K1/116 ,  H05K3/38 ,  H05K3/4644 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/09381 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/2072 ,  H05K2203/0789 ,  H01L2924/00

Abstract: A wiring board includes a first insulating layer coating a first wiring layer. A first through hole is opened in a surface of the first insulating layer and exposes a surface of the first wiring layer. A first via arranged in the first through hole includes an end surface exposed to the surface of the first insulating layer. A gap is formed between the first insulating layer and the first via in the first through hole. A second wiring layer is stacked on the surface of the first insulating layer and the end surface of the first via. The second wiring layer includes a pad filling the gap. The pad is greater in planar shape than the first through hole.

Abstract translation: 布线板包括涂覆第一布线层的第一绝缘层。 第一通孔在第一绝缘层的表面上开放，并露出第一布线层的表面。 布置在第一通孔中的第一通孔包括暴露于第一绝缘层的表面的端表面。 在第一通孔中的第一绝缘层和第一通孔之间形成间隙。 在第一绝缘层的表面和第一通孔的端面上堆叠第二布线层。 第二布线层包括填充间隙的垫。 该垫的平面形状大于第一通孔。

公开(公告)号：US20170033089A1

公开(公告)日：2017-02-02

申请号：US15290232

申请日：2016-10-11

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Makoto AGATANI ,  Toshio HATA ,  Tomokazu NADA ,  Shinya ISHIZAKI

IPC: H01L25/075 ,  H01L33/48 ,  H01L33/62

CPC classification number: H01L25/0753 ,  F21K9/00 ,  F21K9/232 ,  F21V23/06 ,  F21Y2101/00 ,  F21Y2105/10 ,  F21Y2115/10 ,  H01L33/483 ,  H01L33/52 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/01327 ,  H01L2933/0066 ,  H05K1/11 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2201/0979 ,  H05K2201/10106 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light-emitting device capable of ensuring an electric connection between a light-emitting element and an electrode without generating any problem in practical use, by both connecting methods with a solder and a connector, and a lighting device provided with the light-emitting device are provided. The light-emitting device according to the present invention has a plurality of LED chips, and a soldering electrode land and a connector connecting electrode land electrically connected to the chips, on a ceramic substrate. The soldering electrode land is formed of a first conductive material having a function to prevent diffusion to a solder, and the connector connecting electrode land is formed of a second conductive material having a function to prevent oxidation.

Abstract translation: 一种能够确保发光元件和电极之间的电连接而不会在实际使用中产生任何问题的发光装置，通过两种连接方法与焊料和连接器，以及设置有发光装置的照明装置 被提供。 根据本发明的发光装置在陶瓷基板上具有多个LED芯片，以及焊接电极焊盘和与芯片电连接的连接器连接电极焊盘。 焊接电极焊盘由具有防止向焊料扩散的功能的第一导电材料形成，并且连接器连接电极焊盘由具有防止氧化功能的第二导电材料形成。

公开(公告)号：US09554453B2

公开(公告)日：2017-01-24

申请号：US13777369

申请日：2013-02-26

Applicant: MediaTek Inc.

Inventor： Shu-Wei Hsiao

IPC: H05K1/00 ,  H05K1/02

CPC classification number: H05K1/0209 ,  H05K1/0206 ,  H05K2201/09609 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10727 ,  H05K2201/10969

Abstract: A printed circuit board (PCB) structure with a heat dissipation function is provided, including: a package substrate; a landing pad formed over a portion of the package substrate from a first surface thereof, wherein the landing pad has a rectangular configuration and has a plurality of corners; a plurality of ground traces formed over various portions of the package substrate, physically connecting to the bond pad from at least two of the corners thereof, respectively; a first through hole formed through the landing pad and the package substrate from substantially a center portion of the bonding pad; and a plurality of second through holes formed through the landing pad and the package substrate from substantially one of the corners of the bonding pad, wherein the second through holes are adjacent to the ground traces, respectively.

Abstract translation: 提供具有散热功能的印刷电路板（PCB）结构，包括：封装基板; 从所述封装基板的第一表面形成在所述封装基板的一部分上的着陆焊盘，其中所述着陆焊盘具有矩形构造并且具有多个拐角; 形成在所述封装衬底的各个部分上的多个接地迹线，分别从其至少两个角部物理连接到所述接合焊盘; 从接合焊盘的大致中心部分穿过着陆焊盘和封装衬底形成的第一通孔; 以及多个第二通孔，其通过所述着陆焊盘和所述封装基板从所述接合焊盘的大致角部形成，其中所述第二通孔分别与所述接地迹线相邻。

公开(公告)号：US20160353569A1

公开(公告)日：2016-12-01

申请号：US15158777

申请日：2016-05-19

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Jun FURUICHI ,  Noriyoshi SHIMIZU

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K1/0298 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/036 ,  H05K1/0366 ,  H05K1/115 ,  H05K3/0044 ,  H05K3/108 ,  H05K3/426 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0183 ,  H05K2201/0191 ,  H05K2201/0376 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0979 ,  H05K2203/025

Abstract: A wiring substrate includes a core layer having a penetrating hole, a first insulating layer disposed on a first surface of the core layer and having a first opening at a position of the penetrating hole, the first insulating layer containing no filler, a penetrating electrode disposed in the penetrating hole and in the first opening, and a first wiring layer laminated both on the first insulating layer at a first surface thereof facing away from the core layer and on an end face of the penetrating electrode, wherein the first surface of the first insulating layer and the end face of the penetrating electrode are planarized.

Abstract translation: 布线基板包括具有穿透孔的芯层，设置在芯层的第一表面上的第一绝缘层，并且在穿透孔的位置处具有第一开口，第一绝缘层不包含填料，设置穿透电极 在所述贯通孔和所述第一开口中的第一表面以及在所述第一绝缘层上层叠的第一布线层，所述第一布线层在其背离所述芯层的第一表面和所述穿透电极的端面上， 绝缘层和穿透电极的端面被平坦化。

公开(公告)号：US20160353565A1

公开(公告)日：2016-12-01

申请号：US15161731

申请日：2016-05-23

Applicant: CANON KABUSHIKI KAISHA

Inventor： Junichiro Iri ,  Ryo Sato ,  Kazuhiro Idogawa ,  Chiaki Muraoka ,  Hiromasa Amma ,  Takuya Iwano

IPC: H05K1/02 ,  B41J2/14

CPC classification number: H05K1/028 ,  B41J2/14 ,  B41J2/1752 ,  B41J2/1753 ,  B41J2/17553 ,  H05K1/0296 ,  H05K3/0058 ,  H05K2201/09227 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/09663 ,  H05K2201/09727 ,  H05K2201/0979

Abstract: A wire pattern is divided into a plurality of portions in order to provide a circuit board for which very reliably bonding can be achieved and a liquid ejection head including the circuit board.

Abstract translation: 线图案被分成多个部分，以便提供可以实现非常可靠地结合的电路板和包括电路板的液体喷射头。