公开(公告)号：US20140168909A1

公开(公告)日：2014-06-19

申请号：US13719506

申请日：2012-12-19

Applicant: Tieyu Zheng ,  Jin A. Zhao ,  Ru Han ,  Min Pei

Inventor： Tieyu Zheng ,  Jin A. Zhao ,  Ru Han ,  Min Pei

IPC: H05K1/18 ,  H05K1/03

CPC classification number: H05K3/3452 ,  H05K1/111 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/0969 ,  H05K2201/0989 ,  H05K2201/099 ,  Y02P70/611

Abstract: Attachment structures for electrically coupling a microelectronic package to a microelectronic board/interposer including joint pads formed on the microelectronic board/interposer which provide a gap between respective openings in a solder resist layer of the microelectronic substrate and each of the joint pads. Such attachment structures may reduce or substantially eliminate contact between a solder interconnect and a solder resist layer of the microelectronic board/interposer, which may, in turn, reduce or substantially eliminate the potential of crack initiation and propagation at contact areas between the solder interconnect and a solder resist layer of the microelectronic board/interposer due to stresses induced by a mismatch of thermal expansion between the microelectronic package and the microelectronic board/interposer during thermal cycling. Further, the connection area between the pad and outside circuitry may be maximized, so that the impact to electrical performance due to the pad design may be minimized.

Abstract translation: 用于将微电子封装电耦合到包括形成在微电子板/插入件上的接合焊盘的微电子板/插入件的附接结构，其提供微电子衬底的阻焊层中的各个开口之间的间隙以及每个接合焊盘。 这种附接结构可以减少或基本上消除微电子板/插入件的焊料互连和阻焊层之间的接触，这又可以减少或基本消除在焊料互连和焊接互连之间的接触区域处的裂纹发生和传播的可能性 由于在热循环期间微电子封装和微电子板/插入件之间的热膨胀不匹配引起的应力，微电子板/插入件的阻焊层。 此外，焊盘和外部电路之间的连接区域可以最大化，使得由于焊盘设计而对电性能的影响可能被最小化。

公开(公告)号：US08592968B2

公开(公告)日：2013-11-26

申请号：US13563560

申请日：2012-07-31

Applicant: Koujirou Shibuya

Inventor： Koujirou Shibuya

IPC: H01L23/52 ,  H01L23/48

CPC classification number: H05K3/3452 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/0989 ,  H05K2201/10378 ,  Y10T29/49124 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes an interposer having a base member including a first surface and a second surface opposite to the first surface, a first interconnect formed on the first surface of the base member, a first insulating film formed on the first surface of the base member, a first external terminal and a second external terminal neighboring the first external terminal formed on the second surface of the base member, a second interconnect formed on the second surface of the base member and passing between the first external terminal and the second external terminal, and a second insulating film formed on the second surface of the base member, a semiconductor chip mounted on the first insulating film, a sealing resin formed on the first insulating film and sealing the semiconductor chip. The second insulating film has an opening so that the second interconnect is exposed in an area.

Abstract translation: 一种半导体器件，包括：内插件，具有包括第一表面和与第一表面相对的第二表面的基底构件，形成在基底构件的第一表面上的第一互连，形成在基底构件的第一表面上的第一绝缘膜 与第一外部端子相邻的第一外部端子和第二外部端子，形成在基体的第二表面上的第一外部端子，形成在基体的第二表面上并在第一外部端子和第二外部端子之间通过的第二互连， 以及形成在所述基底构件的第二表面上的第二绝缘膜，安装在所述第一绝缘膜上的半导体芯片，形成在所述第一绝缘膜上并密封所述半导体芯片的密封树脂。 第二绝缘膜具有开口，使得第二互连件暴露在一个区域中。

公开(公告)号：US20130277098A1

公开(公告)日：2013-10-24

申请号：US13995208

申请日：2011-12-21

Applicant: Kiyohiro Hine ,  Akio Furusawa ,  Masato Mori

Inventor： Kiyohiro Hine ,  Akio Furusawa ,  Masato Mori

IPC: H05K1/18 ,  H05K13/04

CPC classification number: H05K1/181 ,  B23K1/19 ,  B23K35/0261 ,  B23K35/24 ,  B23K35/262 ,  C22C13/00 ,  H05K3/3442 ,  H05K3/3452 ,  H05K3/3463 ,  H05K3/3484 ,  H05K13/0465 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10636 ,  H05K2203/1476 ,  Y02P70/611 ,  Y02P70/613

Abstract: The present invention has an aspect to provide a mounted structure of which heat-resistant fatigue characteristic is improved. A mounted structure is provided with a substrate having a substrate electrode, an electronic component having a component electrode, and a bonding part bonding the substrate electrode and the component electrode, wherein the bonding part is constituted by a solder reinforcing part and a solder bonding part, the solder reinforcing part is a side vicinity part of the bonding part, and is constituted by In of 3 wt % or more and 8 wt % or less and Sn of 88 wt % or more, and the solder bonding part is constituted by a Sn—Bi system solder material and In of 0 wt % or more and less than 3 wt %.

Abstract translation: 本发明的一个方面是提供一种提高耐热疲劳特性的安装结构。 安装结构设置有具有基板电极的基板，具有部件电极的电子部件和接合基板电极和部件电极的接合部，其中，接合部由焊料增强部和焊接部 焊料加强部是接合部的侧部附近，由3重量％以上且8重量％以下的Sn和88重量％以上的Sn构成，焊接部由 Sn-Bi系焊料和0重量％以上且小于3重量％的In。

公开(公告)号：US08525024B2

公开(公告)日：2013-09-03

申请号：US13063996

申请日：2009-09-30

Applicant: Hiroaki Kaneda ,  Takeshi Yamada

Inventor： Hiroaki Kaneda ,  Takeshi Yamada

IPC: H01J5/00 ,  H01J15/00 ,  H05K5/06 ,  H05K9/00 ,  H05K7/14 ,  H01L23/02

CPC classification number: F16J15/064 ,  H01R13/6599 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/0393 ,  H05K3/28 ,  H05K3/325 ,  H05K9/0018 ,  H05K2201/0314 ,  H05K2201/0715 ,  H05K2201/0989 ,  H05K2203/1147

Abstract: A hermetically sealing device includes a conductive seal member (2) which is integrated with a conductive member (1) extending into a casing (3) and seals a space between the conductive member (1) and an inserting section for the conductive member (1) on the casing (3). In the conductive member (1), an electromagnetic wave shield layer (11) is laminated on a cover film which protects the surface of a base film having a circuit pattern, an insulating layer (12) is laminated on the electromagnetic wave shield layer (11), the insulating layer (12) has an opening section (12a) such that a part of the flat section of the electromagnetic wave shield layer (11) is exposed, and the seal member (2) is integrated with the conductive member (1) to cover the opening section (12a) and is brought into contact with the electromagnetic wave shield layer (11) through the opening section (12a).

Abstract translation: 气密密封装置包括导电密封件（2），导电密封件（2）与延伸到壳体（3）中的导电件（1）成一体并密封导电件（1）与导电件（1）的插入部分之间的空间 ）在壳体（3）上。 在导电部件（1）中，在保护具有电路图案的基膜的表面的覆盖膜上层叠有电磁波屏蔽层（11），绝缘层（12）层叠在电磁波屏蔽层 如图11所示，绝缘层（12）具有使电磁波屏蔽层（11）的平坦部分的一部分露出的开口部（12a），密封部件（2）与导电部件 1）覆盖开口部分（12a）并通过开口部分（12a）与电磁波屏蔽层（11）接触。

公开(公告)号：US08507805B2

公开(公告)日：2013-08-13

申请号：US12362670

申请日：2009-01-30

Applicant: Seiya Fujii

Inventor： Seiya Fujii

IPC: H05K1/16 ,  H01L21/56

CPC classification number: H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/09745 ,  H05K2201/0989 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a wiring board according to the present invention, a substrate, a solder resist provided on the substrate, a land, a wiring line, and a connection portion connecting the wiring line and the land, the connection portion is provided with a recess as a non-flat portion, and is formed to comprise a width greater than a width of the wiring line and smaller than a width (diameter) of the land, the width of the connection portion being gradually increased from the wiring line toward the land.

Abstract translation: 在根据本发明的布线板中，基板，设置在基板上的阻焊剂，焊盘，布线和连接布线和焊盘的连接部分，连接部分设置有作为 非平坦部分，并且形成为包括大于布线的宽度的宽度并且小于焊盘的宽度（直径），连接部分的宽度从布线向着平台逐渐增加。

公开(公告)号：US08344268B2

公开(公告)日：2013-01-01

申请号：US12496017

申请日：2009-07-01

Applicant: Hideyuki Tsujimura ,  Hidenori Miyakawa ,  Atsushi Yamaguchi ,  Hiroe Kowada ,  Koso Matsuno

Inventor： Hideyuki Tsujimura ,  Hidenori Miyakawa ,  Atsushi Yamaguchi ,  Hiroe Kowada ,  Koso Matsuno

IPC: H05K1/11

CPC classification number: H05K3/288 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2201/0989 ,  H05K2203/0783 ,  H05K2203/1322 ,  Y10T29/49146 ,  H01L2224/0401

Abstract: An electronic component packaging structure includes a circuit board, electronic components mounted on the circuit board and a moisture-proof coating layer covering the electronic components. The moisture-proof coating layer is constituted from a polymer material coating having at least two layers of a lower layer and an upper layer, and the polymer material forming the lower layer has higher swelling property and/or solubility to a repairing solvent that is selected from among hydrocarbon-based solvents than the polymer material forming the upper layer.

Abstract translation: 电子部件封装结构包括电路板，安装在电路板上的电子部件和覆盖电子部件的防潮涂层。 防潮涂层由具有至少两层下层和上层的聚合物材料涂层构成，形成下层的聚合物材料具有较高的溶胀性和/或对所选择的修补溶剂的溶解性 与烃类溶剂相比，形成上层的聚合物材料。

公开(公告)号：US20120319273A1

公开(公告)日：2012-12-20

申请号：US13596860

申请日：2012-08-28

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L21/50 ,  H01L23/498

CPC classification number: H05K3/3452 ,  H01L21/4846 ,  H01L21/4853 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/11 ,  H01L2224/11822 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/0989 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.

Abstract translation: 用于倒装芯片互连的焊接掩模具有跨越多个电路元件的公共开口。 焊接掩模允许在互连的再熔融阶段期间焊料的限制，但是在焊接掩模图案化的通用设计规则中。 此外，用于倒装芯片布线的基板包括具有跨越多个电路元件的公共开口的基板。 此外，倒装芯片封装包括具有跨越多个电路元件的公共开口的基板。

公开(公告)号：US08318537B2

公开(公告)日：2012-11-27

申请号：US12757889

申请日：2010-04-09

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L21/00 ,  H01L29/40

CPC classification number: H01L23/49838 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.

Abstract translation: 通过将互连凸块配合到引线或迹线上的窄互连焊盘而不是捕获板上，来制造衬底上的管芯的倒装芯片互连。 窄互连焊盘的宽度小于要连接的裸片上的凸块的基底直径。 此外，倒装芯片封装包括具有附着到有源表面中的互连焊盘的焊料凸块的芯片，以及在芯片附着表面中的导电迹线上具有窄互连焊盘的衬底，其中凸块配合到 痕迹

公开(公告)号：US20120241946A9

公开(公告)日：2012-09-27

申请号：US12961027

申请日：2010-12-06

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/3205

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0901 ,  H01L2224/1134 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81136 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.

Abstract translation: 半导体器件具有在半导体管芯的表面上的接触焊盘上形成有多个凸点的半导体管芯。 凸块可以具有可熔部分和非易熔部分。 在衬底上形成多个导电迹线，其互连位置的宽度大于凸块和接触焊盘之间的接触界面的20％且小于80％的宽度。 这些凸块被结合到互连部位，使得凸块覆盖互连部位的顶表面和侧表面。 围绕半导体管芯和衬底之间的凸块沉积密封剂。 导电迹线具有通过可以放置在衬底上的相邻导电迹线之间的最小间隔确定的间距，并且互连部位的宽度提供等于导电迹线的间距的布线密度。

公开(公告)号：US08258409B2

公开(公告)日：2012-09-04

申请号：US12058040

申请日：2008-03-28

Applicant: Yasuhiro Kohara ,  Kiyoshi Shibata ,  Masayuki Nagamatsu ,  Ryosuke Usui ,  Toshiya Shimizu

Inventor： Yasuhiro Kohara ,  Kiyoshi Shibata ,  Masayuki Nagamatsu ,  Ryosuke Usui ,  Toshiya Shimizu

IPC: H05K1/00

CPC classification number: H05K3/383 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/056 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K3/243 ,  H05K3/3452 ,  H05K2201/09727 ,  H05K2201/09772 ,  H05K2201/0989 ,  H05K2203/0307 ,  H05K2203/0361 ,  H05K2203/049 ,  H05K2203/0542 ,  H05K2203/0723 ,  H05K2203/1152 ,  H05K2203/1476 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Provided are a circuit board with enhanced moisture resist and the method of manufacturing the circuit board, and a circuit device and a method of manufacturing the circuit device. A circuit board of the present invention includes: a substrate; wirings formed on the main surface of the substrate; a cover layer covering the wirings excluding the regions to be connectors; back electrodes formed on the bottom surface of the substrate; and through-hole electrodes formed so as to penetrate the substrate, and thereby connecting the wirings and the back electrodes. On surfaces of each of the wirings in this circuit board, convex portions on the periphery of the substrate are set larger in width than convex portions in a center portion of the substrate. With this configuration, adhesion reliability between the wirings and the cover layer under a thermal cycle load can be enhanced.

Abstract translation: 提供了一种具有增强的抗湿性的电路板和制造该电路板的方法，以及电路装置和该电路装置的制造方法。 本发明的电路板包括：基板; 在基板的主表面上形成的布线; 覆盖除了作为连接器的区域的布线的覆盖层; 形成在基板的底面上的背面电极; 以及形成为穿透基板的通孔电极，从而连接布线和背面电极。 在该电路基板的各配线的表面上，基板周边的凸部的宽度比基板的中央部的凸部的宽度大。 利用这种结构，可以提高热循环负载下的布线与覆盖层之间的粘附可靠性。