公开(公告)号：US09699901B2

公开(公告)日：2017-07-04

申请号：US14016398

申请日：2013-09-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Kai Yao ,  Yongfa Zhu ,  Yingpei Huang

IPC: H05K5/00 ,  H05K1/11 ,  H05K1/02 ,  H05K3/40

CPC classification number: H05K1/117 ,  H05K1/0265 ,  H05K1/0298 ,  H05K3/4046 ,  H05K2201/0919 ,  H05K2201/09481 ,  H05K2201/0979 ,  H05K2201/10416

Abstract: A golden finger and a board edge interconnecting device are disclosed. The golden finger includes a printed circuit board (PCB) surface layer and at least one PCB inner layer, where a metal foil of the PCB inner layer is connected to a metal foil of the PCB surface layer through a current-carrying structure, so that a current-carrying channel of the golden finger passes through the PCB surface layer and the PCB inner layer. The board edge interconnecting device includes the foregoing golden finger. In the embodiments, a current-carrying capacity of a PCB in the golden finger is increased without increasing a size and thickness of a copper foil of the PCB in the golden finger, thereby effectively improving the current-carrying capacity of the PCB in the golden finger.

公开(公告)号：US20170062688A1

公开(公告)日：2017-03-02

申请号：US15249920

申请日：2016-08-29

Applicant: Johnson Electric S.A.

Inventor： Peng ZHU ,  Steven Eric DEAN ,  Jean-Francois ROY

IPC: H01L33/64 ,  H01L33/62

CPC classification number: H01L33/647 ,  F21V29/70 ,  F21Y2115/10 ,  H01L33/62 ,  H05K1/0204 ,  H05K1/056 ,  H05K1/189 ,  H05K2201/0305 ,  H05K2201/10106 ,  H05K2201/10416

Abstract: A thermally-efficient electrical assembly comprising: an electrically-conductive layer; a heat sink layer; an electrically-insulating interconnecting layer interposed between the electrically-conductive layer and heat sink layer; an electrical component in electrical communication with the electrically-conductive layer; and a metallic thermal bridge in thermal communication with the electrical component and in direct contact with the heat sink layer, thereby bypassing the electrically-insulating layer.

Abstract translation: 一种热效率电气组件，包括：导电层; 散热层; 插入在导电层和散热层之间的电绝缘互连层; 与所述导电层电连通的电气部件; 以及与电气部件热连通并与散热层直接接触的金属热桥，由此绕过电绝缘层。

公开(公告)号：US09480141B1

公开(公告)日：2016-10-25

申请号：US14032908

申请日：2013-09-20

Applicant: Junis Hamadeh

Inventor： Junis Hamadeh

IPC: H05K1/02 ,  H01R12/00

CPC classification number: H01R12/00 ,  H05K1/0206 ,  H05K1/021 ,  H05K1/113 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09463 ,  H05K2201/0959 ,  H05K2201/10106 ,  H05K2201/10401 ,  H05K2201/10416

Abstract: A heat sinking rapid assembly semiconductor package comprising an electrically segmented conductive assembly post. The post is fabricated comprising at least two independent electrically conductive segments separated by an electrically isolating element. An electrical component, such as a semiconductor device, is assembled to an upper portion of the conductive post, wherein each contact of the component is in electrical communication with a respective conductive segment. The post can be mechanically pressed, threaded, or mechanically coupled using any other reasonable mechanical interface into a segmented via or plated-through hole of a printed circuit board (PCB). The electrical segments would be in electrical communication with conductive portions of the segmented via to form a complete electrical circuit between the PCB and the electrical component. A thermally conductive element can be integrated into the post to conduct heat away from the semiconductor device to improve performance and reduce failures related to thermal stress.

Abstract translation: 一种散热快速组装半导体封装，包括电分段的导电组件柱。 该柱被制造成包括由电隔离元件隔开的至少两个独立的导电段。 诸如半导体器件的电气部件被组装到导电柱的上部，其中部件的每个触点与相应的导电部分电连通。 可以使用任何其他合理的机械接口将柱机械地压制，螺纹化或机械耦合到印刷电路板（PCB）的分段通孔或电镀通孔中。 电段将与分段通孔的导电部分电连通，以在PCB和电气部件之间形成完整的电路。 导热元件可以集成到柱中以将热量从半导体器件导出，以提高性能并减少与热应力相关的故障。

公开(公告)号：US20160249445A1

公开(公告)日：2016-08-25

申请号：US15050606

申请日：2016-02-23

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Tae-Hong MIN ,  Myung-Sam KANG ,  Jung-Han LEE ,  Young-Gwan KO

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0206 ,  H05K1/0203 ,  H05K1/0204 ,  H05K1/0207 ,  H05K1/0218 ,  H05K1/111 ,  H05K1/181 ,  H05K1/183 ,  H05K3/4608 ,  H05K2201/0323 ,  H05K2201/0338 ,  H05K2201/066 ,  H05K2201/10416

Abstract: A circuit board is disclosed. In addition to insulating layers, the circuit board includes a structure for heat transfer that includes a first layer that is formed of graphite or graphene, a second layer that is formed of metallic material and disposed on one surface of the first layer, and a third layer that is formed of metallic material and disposed on the other surface of the first layer, and at least a portion of the structure for heat transfer is inserted into an insulation layer. Such a circuit board provides improved heat management. Also disclosed is a method of manufacturing the circuit board.

Abstract translation: 公开了一种电路板。 除了绝缘层之外，电路板还包括用于传热的结构，其包括由石墨或石墨烯形成的第一层，由金属材料形成并设置在第一层的一个表面上的第二层，以及第三层 层，其由金属材料形成并且设置在第一层的另一表面上，并且用于传热的结构的至少一部分插入绝缘层中。 这种电路板提供改进的热管理。 还公开了一种制造电路板的方法。

公开(公告)号：US20160218094A1

公开(公告)日：2016-07-28

申请号：US15087200

申请日：2016-03-31

Applicant: Apple Inc.

Inventor： John Bruno ,  Jun Zhai ,  Timothy J. Millet

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/367

CPC classification number: H01L25/18 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/13124 ,  H01L2224/134 ,  H01L2224/13411 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0204 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/09036 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2924/014

Abstract: A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.

Abstract translation: 半导体封装包括耦合到球栅阵列（BGA）衬底的处理器管芯（例如，SoC）和一个或多个存储器管芯（例如，DRAM）。 使用端子（例如，焊球）将处理器管芯和存储器管芯耦合到BGA衬底的相对侧。 可以使用位于处理器管芯的周边周围的一个或多个端子将封装耦合到印刷电路板（PCB）。 PCB可以包括凹部，其中处理器管芯的至少一部分位于凹部中。 将处理器管芯的至少一部分定位在凹部中减小了半导体封装组件的整体高度。 电压调节器还可以与处理器管芯相同侧的BGA衬底耦合，其中至少一部分电压调节器位于距离处理器管芯几毫米的凹槽中。

公开(公告)号：US20160039633A1

公开(公告)日：2016-02-11

申请号：US14768526

申请日：2013-02-21

Applicant: OTIS ELEVATOR COMPANY

Inventor： Andreas Tutat ,  Ibrahim IA Atalmis ,  Herbert Horbrügger ,  Marvin Dehmlow

IPC: B66B1/30 ,  B66B11/00 ,  H01H71/10

CPC classification number: B66B1/302 ,  B66B1/306 ,  B66B1/308 ,  B66B11/002 ,  H01H71/10 ,  H05K1/0206 ,  H05K1/0265 ,  H05K2201/10166 ,  H05K2201/10416 ,  Y02B50/127

Abstract: A drive unit for an elevator system, the drive unit including a multilayer, power circuit board; a first DC link formed in a layer of the power circuit board; a second DC link formed in a layer of the power circuit board; a first switch having a first terminal, the first switch mounted to a surface of the power circuit board; a first via electrically coupling the first terminal to the first DC link; a second switch having a second terminal, the second switch mounted to the surface of the power circuit board; and a second via electrically coupling the second terminal to the second DC link; the first via conducting heat from the first switch to the first DC link; the second via conducting heat from the second switch to the second DC link.

Abstract translation: 一种用于电梯系统的驱动单元，所述驱动单元包括多层电力电路板; 形成在所述电源电路板的层中的第一DC链路; 形成在所述电源电路板的层中的第二DC链路; 具有第一端子的第一开关，所述第一开关安装到所述电源电路板的表面; 第一通路，电连接第一端子到第一DC连接器; 具有第二端子的第二开关，所述第二开关安装到所述电源电路板的表面; 以及第二通孔，其将所述第二端子电耦合到所述第二DC链路; 所述第一通过从所述第一开关传导至所述第一DC链路的热量; 第二通过从第二开关传导到第二DC链路的热量。

公开(公告)号：US09125335B2

公开(公告)日：2015-09-01

申请号：US13862298

申请日：2013-04-12

Applicant: Tong Hsing Electronic Industries, Ltd.

Inventor： Wen-Chung Chiang

IPC: H05K3/20 ,  H05K13/00 ,  H01L23/367 ,  H01L23/373 ,  H05K1/02 ,  H01L33/48 ,  H05K1/03

CPC classification number: H05K13/00 ,  H01L23/3677 ,  H01L23/3735 ,  H01L33/486 ,  H01L33/62 ,  H01L33/64 ,  H01L2224/48227 ,  H01L2224/49107 ,  H01L2924/01322 ,  H05K1/0204 ,  H05K1/0306 ,  H05K2201/0355 ,  H05K2201/10416 ,  Y10T29/49128 ,  Y10T156/10 ,  Y10T156/1056 ,  Y10T156/1057 ,  H01L2924/00

Abstract: A ceramic circuit board for use in packaging an electronic element includes a ceramic-copper plate, and a heat-dissipating unit that is adapted for dissipating heat from the electronic element. The ceramic-copperplate includes a ceramic substrate that has opposite first and second surfaces, and a through-hole formed through the first and second surfaces, a top copper pattern that overlies the first surface of the ceramic substrate and that has at least two conducting portions spaced apart from each other, and a bottom copper layer that underlies the second surface of the ceramic substrate. The heat-dissipating unit includes a heat-dissipating layer that is disposed in the through-hole of the ceramic substrate above the bottom copper layer and that has a thermal conductivity larger than that of the ceramic substrate. A method of making the ceramic circuit board is also disclosed.

Abstract translation: 用于封装电子元件的陶瓷电路板包括陶瓷铜板和适于从电子元件散热的散热单元。 陶瓷铜板包括具有相对的第一表面和第二表面的陶瓷基板和穿过第一和第二表面形成的通孔，顶部铜图案覆盖在陶瓷基板的第一表面上，并且具有至少两个导电部分 彼此间隔开的底部铜层和位于陶瓷基板的第二表面下方的底部铜层。 散热单元包括散热层，该散热层设置在陶瓷基板的贯通孔底部铜层的上方，导热率大于陶瓷基板的导热率。 还公开了制造陶瓷电路板的方法。

公开(公告)号：US20150223318A1

公开(公告)日：2015-08-06

申请号：US14610245

申请日：2015-01-30

Applicant: IBIDEN CO., LTD.

Inventor： Hajime SAKAMOTO

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0206 ,  H01L2224/16227 ,  H05K1/0298 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/4661 ,  H05K2201/094 ,  H05K2201/10416

Abstract: A multilayer wiring board includes a first insulating layer, first conductor patterns formed on the first insulating layer, and a wiring structure formed on the first insulating layer and including a heat sink and second conductor patterns formed on the heat sink such that the wiring structure is positioned adjacent to the first conductor patterns on the first insulating layer.

Abstract translation: 多层布线基板包括第一绝缘层，形成在第一绝缘层上的第一导体图案和形成在第一绝缘层上的布线结构，并且包括形成在散热片上的散热器和第二导体图案，使得布线结构 定位成与第一绝缘层上的第一导体图案相邻。

公开(公告)号：USRE45637E1

公开(公告)日：2015-07-28

申请号：US13492284

申请日：2012-06-08

Applicant: Kalu K. Vasoya

Inventor： Kalu K. Vasoya

IPC: H01K3/10 ,  H05K3/38 ,  H05K3/40

CPC classification number: H05K3/386 ,  H05K1/0271 ,  H05K1/0366 ,  H05K3/38 ,  H05K3/403 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K3/4694 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0323 ,  H05K2201/068 ,  H05K2201/10416 ,  H05K2203/063

Abstract: Methods of manufacturing printed wiring boards including electrically conductive constraining cores that involve a single lamination cycle are disclosed. One example of the method of the invention includes drilling a clearance pattern in an electrically conductive constraining core, arranging the electrically conductive constraining core in a stack up that includes B-stage (semi-cured) layers of dielectric material on either side of the constraining core and additional layers of material arranged to form the at least one functional layer, performing a lamination cycle on the stack up that causes the resin in the B-stage (semi-cured) layers of dielectric to reflow and fill the clearance pattern in the electrically conductive constraining core before curing and drilling plated through holes.

Abstract translation: 公开了包括涉及单层压循环的导电约束芯的印刷线路板的制造方法。 本发明的方法的一个实例包括在导电约束芯中钻出间隙图案，将导电约束芯堆叠起来，其包括在约束的任一侧上的电介质材料的B阶（半固化）层 芯层和另外的材料层，以形成至少一个功能层，在叠层上执行层压循环，导致电介质的B级（半固化）层中的树脂回流并填充在 导电约束芯在固化和钻孔电镀通孔之前。

公开(公告)号：US20150146379A1

公开(公告)日：2015-05-28

申请号：US14551680

申请日：2014-11-24

Applicant: Tesat-Spacecom GmbH & Co. KG

Inventor： Hanspeter KATZ ,  Jochen ARTMANN ,  Eric WOLF ,  Christian RAPP ,  Ulrich KOEGER

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0204 ,  H05K1/0207 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/10416

Abstract: A circuit board includes a plurality of conductive track levels disposed one above the other and insulation layers arranged between each of two adjacent conductive track levels. The circuit board includes a thermally conductive element, which includes ceramic, disposed between a first external insulation layer and a second external insulation layer.

Abstract translation: 电路板包括多个设置在另一个之上的导电轨道水平线和布置在两个相邻导电轨道水平面之间的绝缘层。 电路板包括设置在第一外部绝缘层和第二外部绝缘层之间的包括陶瓷的导热元件。