公开(公告)号：US20140037116A1

公开(公告)日：2014-02-06

申请号：US14044654

申请日：2013-10-02

Applicant: Infineon Technologies AG

Inventor： Wolfgang Friza ,  Thomas Grille ,  Klaus Muemmler ,  Guenter Zieger ,  Carsten Ahrens

IPC: H04R23/00

CPC classification number: H04R23/00 ,  B81B2201/0257 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81C1/00047 ,  B81C1/00936 ,  B81C2201/0109 ,  G01L9/0042 ,  H04R19/005 ,  H04R31/006

Abstract: Embodiments show a method for fabricating a cavity structure, a semiconductor structure, a cavity structure for a semiconductor device and a semiconductor microphone fabricated by the same. In some embodiments the method for fabricating a cavity structure comprises providing a first layer, depositing a carbon layer on the first layer, covering at least partially the carbon layer with a second layer to define the cavity structure, removing by means of dry etching the carbon layer between the first and second layer so that the cavity structure is formed.

Abstract translation: 实施例示出了用于制造空腔结构的方法，半导体结构，用于半导体器件的腔结构和由其制造的半导体麦克风。 在一些实施例中，用于制造空腔结构的方法包括提供第一层，在第一层上沉积碳层，至少部分地覆盖碳层与第二层以限定空腔结构，通过干法蚀刻碳 在第一和第二层之间形成空腔结构。

公开(公告)号：US08497148B2

公开(公告)日：2013-07-30

申请号：US13189057

申请日：2011-07-22

Applicant: Bruce C. S. Chou

Inventor： Bruce C. S. Chou

IPC: H01L21/58 ,  H01L23/48

CPC classification number: B81B3/0018 ,  B81B2203/0307 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0109 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13009 ,  H01L2224/13138 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80931 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L21/76898 ,  H01L2924/01014 ,  H01L2924/00

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract translation: 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。

公开(公告)号：US08344466B2

公开(公告)日：2013-01-01

申请号：US12850548

申请日：2010-08-04

Applicant: Pietro Corona ,  Stefano Losa ,  Ilaria Gelmi ,  Roberto Campedelli

Inventor： Pietro Corona ,  Stefano Losa ,  Ilaria Gelmi ,  Roberto Campedelli

IPC: H01L29/84 ,  H01L21/02

CPC classification number: B81C1/00476 ,  B81B2201/0264 ,  B81B2203/0109 ,  B81B2203/0127 ,  B81C1/00047 ,  B81C2201/0109

Abstract: A process for manufacturing a MEMS device, wherein a bottom silicon region is formed on a substrate and on an insulating layer; a sacrificial region of dielectric is formed on the bottom region; a membrane region, of semiconductor material, is epitaxially grown on the sacrificial region; the membrane region is dug down to the sacrificial region so as to form through apertures; the side wall and the bottom of the apertures are completely coated in a conformal way with a porous material layer; at least one portion of the sacrificial region is selectively removed through the porous material layer and forms a cavity; and the apertures are filled with filling material so as to form a monolithic membrane suspended above the cavity. Other embodiments are directed to MEMS devices and pressure sensors.

Abstract translation: 一种用于制造MEMS器件的方法，其中底部硅区域形成在衬底上和绝缘层上; 电介质的牺牲区形成在底部区域上; 半导体材料的膜区域在牺牲区域上外延生长; 将膜区域向下挖到牺牲区域以形成通孔; 孔的侧壁和底部以保形方式完全涂覆有多孔材料层; 牺牲区域的至少一部分被选择性地通过多孔材料层去除并形成空腔; 并且孔填充有填充材料，以便形成悬浮在空腔上方的整体膜。 其它实施例涉及MEMS器件和压力传感器。

公开(公告)号：US08300299B2

公开(公告)日：2012-10-30

申请号：US13098292

申请日：2011-04-29

Applicant: Ming-Hau Tung ,  Lior Kogut

Inventor： Ming-Hau Tung ,  Lior Kogut

IPC: G02B26/00 ,  H01L21/311

CPC classification number: B81C1/00801 ,  B81B3/001 ,  B81B3/0072 ,  B81B2201/042 ,  B81C2201/0109 ,  B81C2201/017 ,  B81C2201/112 ,  B81C2201/115 ,  G02B26/001 ,  Y10T428/30 ,  Y10T428/31678 ,  Y10T428/31935

Abstract: Methods of forming a protective coating on one or more surfaces of a microelectromechanical device are disclosed comprising the steps of forming a composite layer of a sacrificial material and a protective material, and selectively etching the sacrificial material to form a protective coating. The protective coatings of the invention preferably improve one or more aspects of the performance of the microelectromechanical devices in which they are incorporated. Also disclosed are microelectromechanical devices formed by methods of the invention, and visual display devices incorporating such devices.

Abstract translation: 公开了在微机电装置的一个或多个表面上形成保护涂层的方法，其包括以下步骤：形成牺牲材料和保护材料的复合层，并选择性地蚀刻牺牲材料以形成保护涂层。 本发明的保护性涂层优选地改进了其中并入其中的微机电装置的性能的一个或多个方面。 还公开了通过本发明的方法形成的微机电装置以及包括这种装置的视觉显示装置。

公开(公告)号：US20110316101A1

公开(公告)日：2011-12-29

申请号：US12973430

申请日：2010-12-20

Applicant: Dinh DANG ,  Thai DOAN ,  Jeffrey C. MALING ,  Anthony K. STAMPER

Inventor： Dinh DANG ,  Thai DOAN ,  Jeffrey C. MALING ,  Anthony K. STAMPER

IPC: H01L29/84 ,  G06F17/50 ,  H01L21/302

CPC classification number: B81B3/0072 ,  B81B3/0021 ,  B81B2201/01 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00365 ,  B81C1/00476 ,  B81C1/00619 ,  B81C1/00626 ,  B81C1/00666 ,  B81C2201/0109 ,  B81C2201/013 ,  B81C2201/0167 ,  B81C2201/017 ,  B81C2203/0136 ,  B81C2203/0172 ,  G06F17/5068 ,  G06F17/5072 ,  H01H1/0036 ,  H01H57/00 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/1136 ,  H01L2924/0002 ,  Y10S438/937 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/5313 ,  H01L2924/00

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a plurality of discrete wires on a substrate. The method further includes forming a sacrificial cavity layer on the discrete wires. The method further includes forming trenches in an upper surface of the sacrificial cavity layer. The method further includes filling the trenches with dielectric material. The method further includes depositing metal on the sacrificial cavity layer and on the dielectric material to form a beam with at least one dielectric bumper extending from a bottom surface thereof.

Abstract translation: 形成至少一个微电子机械系统（MEMS）的方法包括在基板上形成多个分立的导线。 该方法还包括在分立导线上形成牺牲腔层。 该方法还包括在牺牲腔层的上表面中形成沟槽。 该方法还包括用电介质材料填充沟槽。 该方法还包括在牺牲腔层和电介质材料上沉积金属以形成具有从其底表面延伸的至少一个介电保险杠的梁。

公开(公告)号：US20110315528A1

公开(公告)日：2011-12-29

申请号：US12977850

申请日：2010-12-23

Applicant: Russell T. HERRIN ,  Jeffrey C. Maling ,  Anthony K. Stamper

Inventor： Russell T. HERRIN ,  Jeffrey C. Maling ,  Anthony K. Stamper

IPC: H01H57/00 ,  G06F17/50 ,  H01L21/56

CPC classification number: B81B3/0072 ,  B81B3/0021 ,  B81B2201/01 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00365 ,  B81C1/00476 ,  B81C1/00619 ,  B81C1/00626 ,  B81C1/00666 ,  B81C2201/0109 ,  B81C2201/013 ,  B81C2201/0167 ,  B81C2201/017 ,  B81C2203/0136 ,  B81C2203/0172 ,  G06F17/5068 ,  G06F17/5072 ,  H01H1/0036 ,  H01H57/00 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/1136 ,  H01L2924/0002 ,  Y10S438/937 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/5313 ,  H01L2924/00

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.

Abstract translation: 形成至少一个微电子机械系统（MEMS）的方法包括在远离梁结构的绝缘体层上形成梁结构和电极。 该方法还包括在光束结构上方并且远离电极形成至少一个牺牲层。 该方法还包括在至少一个牺牲层和电极上形成盖结构。 该方法还包括同时提供穿过盖结构的通气孔以暴露牺牲层并在电极上形成部分通孔。 该方法还包括排出牺牲层以形成空腔。 该方法还包括用材料密封通气孔。 该方法还包括通过部分通孔在盖结构中形成最终通孔至电极。

公开(公告)号：US07993949B2

公开(公告)日：2011-08-09

申请号：US12488854

申请日：2009-06-22

Applicant: François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

Inventor： François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

IPC: H01L21/02

CPC classification number: B81C1/00595 ,  B81B2201/0271 ,  B81C2201/0109 ,  B81C2201/014

Abstract: The invention relates to a method of making a component from a heterogeneous substrate comprising first and second portions in at least one monocrystalline material, and a sacrificial layer constituted by at least one stack of at least one layer of monocrystalline Si situated between two layers of monocrystalline SiGe, the stack being disposed between said first and second portions of monocrystalline material, wherein the method consists in etching said stack by making: e) at least one opening in the first and/or second portion and the first and/or second layer of SiGe so as to reach the layer of Si; and f) eliminating all or part of the layer of Si.

Abstract translation: 本发明涉及一种从包含至少一种单晶材料中的第一和第二部分的异质衬底制备组分的方法，以及由位于两层单晶之间的至少一层单晶硅的至少一个叠层构成的牺牲层 SiGe，堆叠设置在单晶材料的第一和第二部分之间，其中该方法包括通过以下步骤蚀刻所述堆叠：e）在第一和/或第二部分中的至少一个开口，以及第一和/ SiGe，以达到Si层; 和f）消除Si的全部或部分层。

公开(公告)号：US07875483B2

公开(公告)日：2011-01-25

申请号：US11462225

申请日：2006-08-03

Applicant: Konami Izumi ,  Mayumi Yamaguchi ,  Fuminori Tateishi

Inventor： Konami Izumi ,  Mayumi Yamaguchi ,  Fuminori Tateishi

IPC: H01L21/00

CPC classification number: B81C1/0015 ,  B81B2203/0118 ,  B81C1/00404 ,  B81C2201/0109

Abstract: To provide a method of easily forming a three-dimensional structure typified by a cantilever by using a thin film formed over an insulating surface, and provide a microelectromechanical system formed by such a method. A three-dimensional structure typified by a cantilever is formed by using a mask having a nonuniform thickness. Specifically, a microstructure is manufactured by processing a structural layer formed over a sacrificial layer by using a mask having a nonuniform thickness and then removing the sacrificial layer. The sacrificial layer can be formed by using a silicon layer or a metal layer.

Abstract translation: 提供通过使用形成在绝缘表面上的薄膜来容易地形成以悬臂为代表的三维结构的方法，并提供通过这种方法形成的微机电系统。 通过使用具有不均匀厚度的掩模形成由悬臂代表的三维结构。 具体地，通过使用具有不均匀厚度的掩模，然后去除牺牲层，通过加工在牺牲层上形成的结构层来制造微结构。 牺牲层可以通过使用硅层或金属层形成。

公开(公告)号：US20100227437A1

公开(公告)日：2010-09-09

申请号：US11385528

申请日：2006-03-21

Applicant: Benzhong Wang ,  Soo Jin Chua

Inventor： Benzhong Wang ,  Soo Jin Chua

IPC: H01L21/56

CPC classification number: B81C1/00047 ,  B81B2207/056 ,  B81C2201/0109 ,  H01L33/18 ,  H01S5/1042 ,  H01S5/1071

Abstract: A method for fabricating an array of semiconductor devices comprising the steps of providing a non-metallic substrate, placing a layer of spheres on said substrate, reducing diameter of the spheres, encapsulating the spheres in a matrix of rigid material, finishing an upper surface of said matrix to expose a portion of said spheres, removing the spheres to form an array of cavities within said matrix, and forming features in said cavities in contact with said substrate so as to form the device.

Abstract translation: 一种用于制造半导体器件阵列的方法，包括以下步骤：提供非金属基底，将一层球体放置在所述基底上，减小所述球体的直径，将所述球体包封在刚性材料的基体中， 所述基体暴露所述球体的一部分，去除所述球体以在所述基体内形成空腔阵列，以及在与所述基底接触的所述空腔中形成特征以形成所述装置。

公开(公告)号：US07763546B2

公开(公告)日：2010-07-27

申请号：US11462026

申请日：2006-08-02

Applicant: Manish Kothari ,  Jeffrey B. Sampsell

Inventor： Manish Kothari ,  Jeffrey B. Sampsell

IPC: H01L21/302

CPC classification number: B81C1/00579 ,  B81C2201/0109 ,  B81C2201/0132

Abstract: Provided herein are methods for preventing the formation and accumulation of surface-associated charges, and deleterious effects associated therewith, during the manufacture of a MEMS device. In some embodiments, methods provided herein comprise etching a sacrificial material in the presence of an ionized gas, wherein the ionized gas neutralizes charged species produced during the etching process and allows for their removal along with other etching byproducts. Also disclosed are microelectromechanical devices formed by methods of the invention, and visual display devices incorporating such devices.

Abstract translation: 本文提供了在制造MEMS器件期间防止表面相关电荷的形成和累积以及与其相关的有害影响的方法。 在一些实施例中，本文提供的方法包括在存在电离气体的情况下蚀刻牺牲材料，其中电离气体中和在蚀刻工艺期间产生的带电物质，并允许其与其它蚀刻副产物一起去除。 还公开了通过本发明的方法形成的微机电装置以及包括这种装置的视觉显示装置。