公开(公告)号：US20140347836A1

公开(公告)日：2014-11-27

申请号：US14455052

申请日：2014-08-08

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Youko NAKAMURA ,  Norihiro NASHIDA

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0296 ,  H01L21/56 ,  H01L21/563 ,  H01L23/12 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/01 ,  H01L25/072 ,  H01L31/048 ,  H01L33/52 ,  H01L33/56 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K1/115 ,  H05K1/185 ,  H05K2201/09609 ,  H05K2201/09727 ,  H05K2201/098 ,  H01L2924/00

Abstract: A semiconductor device includes: a conductive-patterned insulating substrate; conductive blocks fixed to conductive patterns of the conductive-patterned insulating substrate; a semiconductor chip fixed to each conductive block; a printed circuit board that has a conductive post fixed to the semiconductor chip; and a resin. The semiconductor device is configured such that the average volume of a conductive film per unit area of each conductive pattern around a section thereof, to which the corresponding conductive block is fixed, is reduced from the conductive block toward the outside.

Abstract translation: 半导体器件包括：导电图案化绝缘基板; 导电块固定到导电图案化的绝缘衬底的导电图案上; 固定到每个导电块的半导体芯片; 印刷电路板，其具有固定到所述半导体芯片的导电柱; 和树脂。 半导体器件被配置为使得相应的导电块固定到其周围的每个导电图案的每单位面积的导电膜的平均体积从导电块朝向外部减小。

公开(公告)号：US08786099B2

公开(公告)日：2014-07-22

申请号：US13593752

申请日：2012-08-24

Applicant: Tomoharu Fujii

Inventor： Tomoharu Fujii

IPC: H01L23/52 ,  H01L23/538

CPC classification number: H01L23/5386 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16237 ,  H01L2225/107 ,  H01L2924/15311 ,  H05K1/0222 ,  H05K3/3436 ,  H05K3/4602 ,  H05K2201/09609 ,  H05K2201/10378 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A wiring substrate includes: a substrate body made of an inorganic material; a first electrode portion, having a rectangular plane shape, which penetrates through the substrate body in a thickness direction of the substrate body; a second electrode portion, having a rectangular plane shape, which penetrates through the substrate body in the thickness direction and faces the first electrode portion at a prescribed interval; and a signal electrode, which is provided between the first electrode portion and the second electrode portion and penetrates through the substrate body in the thickness direction, wherein one of the first electrode portion and the second electrode portion is a ground electrode and the other is a power electrode.

Abstract translation: 布线基板包括：由无机材料制成的基板主体; 具有矩形平面形状的第一电极部分，其沿着所述基板主体的厚度方向穿过所述基板主体; 具有矩形平面形状的第二电极部分，其在厚度方向上穿过基板主体并以规定的间隔面对第一电极部分; 以及信号电极，其设置在所述第一电极部分和所述第二电极部分之间，并且在所述厚度方向上穿过所述基板主体，其中所述第一电极部分和所述第二电极部分中的一个是接地电极，而另一个是 电源电极。

公开(公告)号：US20140076844A1

公开(公告)日：2014-03-20

申请号：US14080549

申请日：2013-11-14

Applicant: Second Sight Medical Products, Inc.

Inventor： Jerry Ok ,  Robert J. Greenberg

IPC: H05K3/46 ,  H05K3/12 ,  B32B37/14

CPC classification number: H05K3/4061 ,  B32B37/14 ,  C04B35/10 ,  C04B37/00 ,  C04B2237/064 ,  H05K1/0306 ,  H05K3/0044 ,  H05K3/0047 ,  H05K3/005 ,  H05K3/12 ,  H05K3/1225 ,  H05K3/1233 ,  H05K3/4614 ,  H05K3/4623 ,  H05K3/4629 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2203/1147 ,  H05K2203/308 ,  Y10T156/10

Abstract: A method for fabricating a biocompatible hermetic housing including electrical feedthroughs, the method comprises providing a ceramic sheet having an upper surface and a lower surface, forming at least one via hole in said ceramic sheet extending from said upper surface to said lower surface, inserting a conductive thick film paste into said via hole, laminating the ceramic sheet with paste filled via hole between an upper ceramic sheet and a lower ceramic sheet to foam a laminated ceramic substrate, firing the laminated ceramic substrate to a temperature to sinter the laminated ceramic substrate and cause the paste filled via hole to form metalized via and cause the laminated ceramic substrate to form a hermetic seal around said metalized via, and removing the upper ceramic sheet and the lower ceramic sheet material from the fired laminated ceramic substrate to expose an upper and a lower surface of the metalized via.

Abstract translation: 一种制造包括电馈通件的生物相容性密封壳体的方法，所述方法包括提供具有上表面和下表面的陶瓷片，在从所述上表面延伸到所述下表面的所述陶瓷片中形成至少一个通孔，插入 将导电性厚膜糊剂进入所述通孔中，在上陶瓷片和下陶瓷片之间通过孔填充陶瓷片层压陶瓷片，以使层叠陶瓷基板发泡，将层叠陶瓷基板烧结至烧结层叠陶瓷基板的温度， 使填充通孔的糊料形成金属化通孔，并使层压陶瓷基板在所述金属化通孔周围形成气密密封，并从烧结的层叠陶瓷基板上除去上陶瓷片和下陶瓷片材以暴露上层和 金属化通孔的下表面。

公开(公告)号：US08642908B2

公开(公告)日：2014-02-04

申请号：US13202176

申请日：2010-10-13

Applicant: Jonas Moran ,  Mats Kleverman

Inventor： Jonas Moran ,  Mats Kleverman

IPC: H03K17/975

CPC classification number: G06F3/0202 ,  H03K17/9645 ,  H05K1/0275 ,  H05K1/053 ,  H05K1/115 ,  H05K1/116 ,  H05K1/162 ,  H05K1/167 ,  H05K3/0026 ,  H05K3/4015 ,  H05K3/4046 ,  H05K3/445 ,  H05K2201/0108 ,  H05K2201/0376 ,  H05K2201/09545 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/0999 ,  H05K2201/10121 ,  H05K2201/10151 ,  H05K2203/107

Abstract: An electronic device comprises a housing having an outer face and an inner face. A key is provided on the housing, which comprises a micro hole formed in the housing and a conductive material extending within the micro hole to the outer face of the housing. A sensor is coupled to the conductive material to detect whether an object is brought into contact or out of contact with the micro hole at the outer face.

Abstract translation: 电子设备包括具有外表面和内表面的壳体。 在壳体上设有钥匙，该钥匙包括形成在壳体中的微孔和在微孔内延伸到壳体外表面的导电材料。 传感器耦合到导电材料，以检测物体是否与外表面的微孔接触或脱离接触。

公开(公告)号：US08598467B2

公开(公告)日：2013-12-03

申请号：US13275808

申请日：2011-10-18

Applicant: Kevin C. Olson ,  Alan G. Wang

Inventor： Kevin C. Olson ,  Alan G. Wang

IPC: H05K1/11

CPC classification number: H01L21/486 ,  C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/142 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  H01L2924/00

Abstract: A process for fabricating a multi-layer circuit assembly is provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; (c) removing the dielectric coating in a predetermined pattern to expose sections of the substrate; (d) applying a layer of metal to all surfaces to form metallized vias through and/or to the electrically conductive core; (e) applying a resist to the metal layer to form a photosensitive layer thereon; (f) imaging resist in predetermined locations; (g) developing resist to uncover selected areas of the metal layer; and (h) etching uncovered areas of metal to form an electrical circuit pattern connected by the metallized vias.

Abstract translation: 提供了一种用于制造多层电路组件的工艺。 该方法包括（a）提供基底，其至少一个区域包括通孔密度为500至10,000个孔/平方英寸（75至1550个孔/平方厘米）的多个通孔区域; （b）将介电涂层施加到所述基底的所有暴露表面上以在其上形成保形涂层; （c）以预定图案去除所述电介质涂层以暴露所述基板的部分; （d）将金属层施加到所有表面以形成通过和/或导电芯的金属化通孔; （e）在所述金属层上施加抗蚀剂以在其上形成感光层; （f）在预定位置的成像抗蚀剂; （g）显影抗蚀剂以露出金属层的选定区域; 和（h）蚀刻金属的未覆盖区域以形成通过金属化通孔连接的电路图案。

公开(公告)号：US20130062754A1

公开(公告)日：2013-03-14

申请号：US13593752

申请日：2012-08-24

Applicant: Tomoharu Fujii

Inventor： Tomoharu Fujii

IPC: H05K1/11 ,  H01L23/48

CPC classification number: H01L23/5386 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16237 ,  H01L2225/107 ,  H01L2924/15311 ,  H05K1/0222 ,  H05K3/3436 ,  H05K3/4602 ,  H05K2201/09609 ,  H05K2201/10378 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A wiring substrate includes: a substrate body made of an inorganic material; a first electrode portion, having a rectangular plane shape, which penetrates through the substrate body in a thickness direction of the substrate body; a second electrode portion, having a rectangular plane shape, which penetrates through the substrate body in the thickness direction and faces the first electrode portion at a prescribed interval; and a signal electrode, which is provided between the first electrode portion and the second electrode portion and penetrates through the substrate body in the thickness direction, wherein one of the first electrode portion and the second electrode portion is a ground electrode and the other is a power electrode.

Abstract translation: 布线基板包括：由无机材料制成的基板主体; 具有矩形平面形状的第一电极部分，其沿着所述基板主体的厚度方向穿过所述基板主体; 具有矩形平面形状的第二电极部分，其在厚度方向上穿过基板主体并以规定的间隔面对第一电极部分; 以及信号电极，其设置在所述第一电极部分和所述第二电极部分之间，并且在所述厚度方向上穿过所述基板主体，其中所述第一电极部分和所述第二电极部分中的一个是接地电极，而另一个是 电源电极。

公开(公告)号：US08166643B2

公开(公告)日：2012-05-01

申请号：US12702865

申请日：2010-02-09

Applicant: Kiyoshi Shibata ,  Ryosuke Usui ,  Yasunori Inoue

Inventor： Kiyoshi Shibata ,  Ryosuke Usui ,  Yasunori Inoue

IPC: H05K3/36

CPC classification number: H05K3/445 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/44 ,  H05K2201/0382 ,  H05K2201/09054 ,  H05K2201/09609 ,  H05K2201/0969 ,  H05K2203/0323 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: A method of manufacturing a circuit apparatus includes forming a plurality of pierced holes in a metal substrate. A first wiring layer is formed on one side of the metal substrate via a first insulating layer, and a second wiring layer is formed on the other side of the metal substrate via a second insulating layer. A conductor layer is formed in at least some of the plurality of pierced holes to establish a connection between the first wiring layer and the second wiring layer. A circuit element is connected to the first wiring layer on the one side of the metal substrate. When a plurality of pierced holes are formed, protrusions are formed on a surface of the metal substrate at least along either edge of each of the pierced holes provided with the conductor layer to protrude in a convex manner from the surface of the metal substrate.

Abstract translation: 电路装置的制造方法包括在金属基板上形成多个穿孔。 第一布线层经由第一绝缘层在金属基板的一侧上形成，并且第二布线层经由第二绝缘层形成在金属基板的另一侧上。 在多个穿孔中的至少一些穿孔中形成导体层，以建立第一布线层和第二布线层之间的连接。 电路元件连接到金属基板的一侧上的第一布线层。 当形成多个穿孔时，至少沿着设置有导体层的每个穿孔的任一边缘，在金属基板的表面上形成突起，以从金属基板的表面凸出突出。

公开(公告)号：US08138609B2

公开(公告)日：2012-03-20

申请号：US12832177

申请日：2010-07-08

Applicant: Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

Inventor： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

IPC: H01L23/48

CPC classification number: H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/0116 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10674 ,  H05K2203/0315 ,  H05K2203/1142 ,  H01L2924/00

Abstract: In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole.

Abstract translation: 在半导体器件中，衬底包括从衬底的顶表面到底表面穿透衬底的多个线导体。 半导体芯片固定在基板的孔中。 在衬底和半导体芯片的顶表面上形成第一绝缘层。 第一布线层形成在第一绝缘层上，并且经由第一绝缘层的通孔与半导体芯片电连接，一些线导体暴露于一个通孔。 在基板和半导体芯片的底面上形成第二绝缘层。 第二布线层形成在第二绝缘层上，并且经由第二绝缘层的通孔与暴露于通孔的一些线导体电连接。

公开(公告)号：US08129625B2

公开(公告)日：2012-03-06

申请号：US10551439

申请日：2004-04-06

Applicant: Shinobu Kato

Inventor： Shinobu Kato

IPC: H05K1/16

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09609 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: In a core substrate 30, a ground through hole 36E and a power through hole 36P are disposed in the grid formation, so that electromotive force induced in X direction and Y direction cancel out each other. As a result, even if mutual inductance is reduced and a high frequency IC chip is loaded, electric characteristic and reliability can be improved without generating malfunction or error.

Abstract translation: 在芯基板30中，在栅格形成中设置有接地贯通孔36E和电力通孔36P，使得在X方向和Y方向上感应的电动势相互抵消。 结果，即使减小互感并且加载高频IC芯片，也可以提高电特性和可靠性而不产生故障或错误。

公开(公告)号：US20120048703A1

公开(公告)日：2012-03-01

申请号：US12923098

申请日：2010-09-01

Applicant: Michael Kotson ,  Eric Sidle ,  Gregory Harold Thamm

Inventor： Michael Kotson ,  Eric Sidle ,  Gregory Harold Thamm

IPC: H01H13/76 ,  H05K1/11

CPC classification number: H05K1/115 ,  G06F3/0202 ,  H01H2239/004 ,  H01H2239/018 ,  H05K1/0218 ,  H05K2201/0715 ,  H05K2201/09481 ,  H05K2201/09609 ,  H05K2201/10053

Abstract: A printed circuit board, especially for a computer keypad, and method for avoiding electromagnetic interference include conductive signal traces positioned on a surface of one of a nonconductive layer that is other than the outward facing surface of an outer nonconductive layer, and vertical interconnect accesses extending through the outer nonconductive layer and connecting the signal traces to the outward facing surface of the outer nonconductive layer, wherein each vertical interconnect access includes a conductive portion on the outward facing surface of the outer nonconductive layer, and the conductive portion has an area no greater than 1/10 the area of the asociated signal trace. Keys selectively connect pairs of vertical interconnect accesses.

Abstract translation: 特别是用于计算机键盘的印刷电路板以及用于避免电磁干扰的方法包括定位在非导电层之一的非导电层之外的导电信号迹线，该非导电层不是外部非导电层的面向外的表面，并且垂直互连通路延伸 通过外部非导电层并将信号迹线连接到外部非导电层的面向外的表面，其中每个垂直互连通路包括在外部非导电层的面向外的表面上的导电部分，并且导电部分的面积不大 超过1/10的相关信号迹线的面积。 键选择性地连接垂直互连接口对。