公开(公告)号：US20110061911A1

公开(公告)日：2011-03-17

申请号：US12654372

申请日：2009-12-17

Applicant: Hyung Jin Jeon ,  Jong In Ryu ,  Seung Wan Shin ,  Seon Hee Moon ,  Young Do Kweon ,  Seung Wook Park

Inventor： Hyung Jin Jeon ,  Jong In Ryu ,  Seung Wan Shin ,  Seon Hee Moon ,  Young Do Kweon ,  Seung Wook Park

IPC: H05K1/03 ,  B05D5/12

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2225/06572 ,  H01L2924/0002 ,  H05K3/244 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/0979 ,  H05K2201/10378 ,  H01L2924/00

Abstract: An interposer includes: an insulation plate where a via is formed, the insulation plate including a resin or a ceramic; a first upper redistribution layer electrically connected to the via along a circuit pattern designed on the top surface of the insulation plate; a first upper protection layer laminated to expose a portion of the first upper redistribution layer and protecting the first upper redistribution layer; a second upper redistribution layer electrically connected to the first upper redistribution layer and laminated along a designed circuit pattern designed; a second upper protection layer laminated to expose a portion of the second upper redistribution layer and protecting the second upper redistribution layer; and an under bump metallization (UBM) formed at the exposed portion of the second upper redistribution layer.

Abstract translation: 插入件包括：形成通孔的绝缘板，绝缘板包括树脂或陶瓷; 沿着设计在绝缘板的顶表面上的电路图案电连接到通孔的第一上再分配层; 层叠以暴露第一上再分布层的一部分并保护第一上再分布层的第一上保护层; 电连接到第一上再分配层并沿着设计的设计电路图案层压的第二上再分布层; 层压以暴露第二上再分布层的一部分并保护第二上再分布层的第二上保护层; 以及形成在第二上再分布层的暴露部分处的凸块下金属化（UBM）。

公开(公告)号：US20110057324A1

公开(公告)日：2011-03-10

申请号：US12941511

申请日：2010-11-08

Applicant: Hideki Kotake ,  Kiyoshi Hyodo ,  Inetaro Kurosawa ,  Yukio Hashimoto ,  Toku Yoshino ,  Tomoo Iijima

Inventor： Hideki Kotake ,  Kiyoshi Hyodo ,  Inetaro Kurosawa ,  Yukio Hashimoto ,  Toku Yoshino ,  Tomoo Iijima

IPC: H01L23/522

CPC classification number: H05K3/4038 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/20 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4647 ,  H05K3/4658 ,  H05K2201/0379 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1536 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An interconnect element is provided. A monolithic dielectric element has a first exposed major surface, a plurality of first recesses extending inwardly from the first major surface, and a second exposed major surface remote from the first major surface, a plurality of second recesses extending inwardly from the second major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses and extend in one or more directions along the first major surface. A plurality of second metal interconnect patterns are embedded in the plurality of second recesses and extend in one or more directions along the second major surface. A plurality of non-hollow metal posts extend through the dielectric element between at least some of the plurality of first metal interconnect patterns and at least some of the plurality of second metal interconnect patterns.

Abstract translation: 提供互连元件。 单片电介质元件具有第一暴露的主表面，从第一主表面向内延伸的多个第一凹槽和远离第一主表面的第二暴露的主表面，从第二主表面向内延伸的多个第二凹槽。 多个第一金属互连图案被嵌入在多个第一凹部中并沿着第一主表面沿一个或多个方向延伸。 多个第二金属互连图案被嵌入在多个第二凹部中并沿着第二主表面沿一个或多个方向延伸。 多个非中空金属柱在多个第一金属互连图案中的至少一些和多个第二金属互连图案中的至少一些之间延伸穿过介质元件。

公开(公告)号：US20110053392A1

公开(公告)日：2011-03-03

申请号：US12856940

申请日：2010-08-16

Applicant: Yoshihiro IHARA

Inventor： Yoshihiro IHARA

IPC: H01R12/30

CPC classification number: H01R12/57 ,  H01R13/2435 ,  H05K3/32 ,  H05K3/4092 ,  H05K2201/0311 ,  H05K2201/0949 ,  H05K2201/1031 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10962 ,  Y02P70/611

Abstract: Connection terminals each include: a bonding portion bonded to a pad of a substrate; a contacting portion disposed to face the bonding portion; a spring portion present between the bonding portion and the contacting portion; and an engaging portion engaged with a portion of a slit provided in a plate-like member. These constituent portions of the connection terminal are formed integrally with each other. The plate-like member has recessed portions formed at predetermined positions, and the connection terminals are electrically connected to the pads of the substrate with the bonding portions of the connection terminals being locked to the recessed portions.

Abstract translation: 连接端子各自包括：结合到基板的焊盘的接合部分; 接触部，设置成面对所述接合部; 存在于所述接合部和所述接触部之间的弹簧部; 以及与设置在板状构件中的狭缝的一部分接合的接合部。 连接端子的这些构成部分彼此一体地形成。 板状构件具有形成在预定位置的凹部，连接端子与基板的焊盘电连接，连接端子的接合部分被锁定到凹部。

公开(公告)号：US07845954B2

公开(公告)日：2010-12-07

申请号：US11995339

申请日：2006-04-17

Applicant: Yoshihiro Tomura ,  Yasushi Nakagiri ,  Kunio Hibino ,  Yoshihiko Yagi ,  Akihiro Miyashita ,  Masahiro Ono ,  Masato Mori

Inventor： Yoshihiro Tomura ,  Yasushi Nakagiri ,  Kunio Hibino ,  Yoshihiko Yagi ,  Akihiro Miyashita ,  Masahiro Ono ,  Masato Mori

IPC: H01R12/00

CPC classification number: H01R12/00 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/1627 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0284 ,  H05K1/144 ,  H05K1/145 ,  H05K3/28 ,  H05K3/284 ,  H05K3/368 ,  H05K3/403 ,  H05K2201/09018 ,  H05K2201/09845 ,  H05K2201/09909 ,  H05K2201/10378 ,  H05K2201/2018 ,  Y10T29/49117 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A first circuit board (1) mounted with an electronic component (16) and a second circuit board (2) are vertically connected three-dimensionally through an interconnecting board (3) wherein the terminal portion (6) of the land electrode (5) on the interconnecting board (3) is buried in the termination material (9) of the interconnecting board (3). Consequently, the chance of peeling or cracking due to peeling stress or shearing stress acting between the upper/lower circuit boards and the land electrode by high density mounting, thermal shock or falling impact can be suppressed or buffered resulting in high reliability.

Abstract translation: 安装有电子部件（16）和第二电路板（2）的第一电路板（1）通过互连板（3）垂直连接，其中焊盘电极（5）的端子部分（6） 在互连板（3）上的埋设在互连板（3）的端接材料（9）中。 因此，可以抑制或缓冲由于高密度安装，热冲击或落下冲击而在上下电路板和焊盘电极之间作用的剥离应力或剪切应力的剥离或破裂的机会，从而导致高可靠性。

公开(公告)号：US07841862B2

公开(公告)日：2010-11-30

申请号：US10547003

申请日：2004-02-27

Applicant: Miki Hasegawa

Inventor： Miki Hasegawa

IPC: H01R1/00

CPC classification number: H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/023 ,  H05K1/162 ,  H05K3/325 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0314 ,  H05K2201/10378 ,  H05K2203/0235 ,  H01L2924/00

Abstract: To provide a dielectric sheet that can be used as an elastomer connector in order to connect highly integrated circuit board and fine pitch electronic parts. The dielectric sheet (10f) comprises a first penetrating region (222c) having high permittivity, and a second penetrating region (33a) having conductivity, the regions are arranged and formed in such a way that they are alternatively interspersed in longitudinal and crosswise directions in a non-conductive sheet-shaped elastomer. The transverse thickness W2 and longitudinal thickness W5 in the first penetrating region (222c) may be arbitrarily determined. Similarly, the transverse thickness W3 and longitudinal thickness W5 in the second penetrating region (33a) may be arbitrarily determined. The dielectric sheet (10f) serves to compliment the circuit of electronic parts (for example, the printing board) to be connected thereto.

Abstract translation: 为了提供可以用作弹性体连接器以便连接高度集成的电路板和细间距电子部件的电介质片。 电介质片（10f）包括具有高介电常数的第一穿透区域（222c）和具有导电性的第二穿透区域（33a），这些区域被布置和形成为使得它们交替地沿纵向和横向方向散布在 非导电性片状弹性体。 第一穿透区域（222c）中的横向厚度W2和纵向厚度W5可以任意确定。 类似地，第二穿透区域（33a）中的横向厚度W3和纵向厚度W5可以任意确定。 电介质片（10f）用于补充与其连接的电子部件（例如印刷基板）的电路。

公开(公告)号：US07823274B2

公开(公告)日：2010-11-02

申请号：US11905188

申请日：2007-09-28

Applicant: Frank D. Egitto ,  Voya R. Markovich ,  Luis J. Matienzo

Inventor： Frank D. Egitto ,  Voya R. Markovich ,  Luis J. Matienzo

IPC: H05K3/46

CPC classification number: H05K3/462 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/445 ,  H05K2201/015 ,  H05K2201/0245 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of making a multilayered circuitized substrate assembly which includes bonding at least two circuitized substrates each including at least one layer of high temperature dielectric material, one of these layers in turn including at least one thru-hole therein having therein a quantity of a a low temperature conductive paste, the paste including an organic binder component and at least one metallic component. The flakes of the metallic component are sintered during the bonding to form a conductive path through the dielectric of one of the substrates.

Abstract translation: 一种制造多层电路化基板组件的方法，该方法包括粘合至少两个电路化基板，每个电路基板包括至少一层高温介电材料，这些层中的一个依次包括至少一个其中具有一定数量的低电介质材料的通孔 所述膏体包含有机粘合剂成分和至少一种金属成分。 金属部件的薄片在接合期间被烧结以形成通过其中一个基板的电介质的导电路径。

公开(公告)号：US20100244871A1

公开(公告)日：2010-09-30

申请号：US12709619

申请日：2010-02-22

Applicant: James L. Blair ,  David W. Waite ,  Ashish Lohiya ,  Saritha Narra ,  Jeffrey T. Smith ,  Arvid G. Sammuli

Inventor： James L. Blair ,  David W. Waite ,  Ashish Lohiya ,  Saritha Narra ,  Jeffrey T. Smith ,  Arvid G. Sammuli

IPC: G01R31/02 ,  H01R12/14

CPC classification number: H05K1/112 ,  G01R1/07378 ,  G01R31/2889 ,  H05K1/0219 ,  H05K2201/0314 ,  H05K2201/09309 ,  H05K2201/09418 ,  H05K2201/09609 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2203/167

Abstract: Space transformer connectors for coupling printed circuit boards and/or other electrical connections are disclosed. A scalar design of a multilayer space transformer connector allows for a variety of pad-array field connections. A conductive elastomer interface provides for repeated and consistent coupling and decoupling of the space transformer connector.

Abstract translation: 公开了用于耦合印刷电路板和/或其它电连接的空间变压器连接器。 多层空间变压器连接器的标量设计允许各种焊盘阵列现场连接。 导电弹性体接口提供空间变压器连接器的重复和一致的耦合和去耦。

公开(公告)号：US20100243298A1

公开(公告)日：2010-09-30

申请号：US12414122

申请日：2009-03-30

Applicant: Vadim Gektin ,  David W. Copeland

Inventor： Vadim Gektin ,  David W. Copeland

IPC: H05K1/14 ,  H01B5/00

CPC classification number: H05K3/325 ,  B82Y10/00 ,  H01R12/7082 ,  H05K2201/026 ,  H05K2201/10378

Abstract: In at least one embodiment, an interposer for a board interconnect system is provided. The interposer comprises a frame and at least one interconnect. The frame receives a substrate. The substrate includes a top side, a bottom side, and a conductive interface. The conductive interface extends through the top side and the bottom side for delivering an electrical signal from an electrical device positioned on the top side therethrough. The at least one interconnect includes a plurality of carbon nanotubes (CNTs) positioned within the frame for contacting the conductive interface of the substrate to deliver the electrical signal to a conductive arrangement of a circuit board.

Abstract translation: 在至少一个实施例中，提供了用于板互连系统的插入器。 插入器包括框架和至少一个互连件。 框架接收基板。 基板包括顶侧，底侧和导电界面。 导电接口延伸穿过顶侧和底侧，用于从位于顶侧的电气装置传送电信号。 所述至少一个互连件包括位于所述框架内的多个碳纳米管（CNT），用于接触所述基板的所述导电接口以将所述电信号传送到电路板的导电布置。

公开(公告)号：US20100230145A1

公开(公告)日：2010-09-16

申请号：US12521558

申请日：2007-12-28

Applicant: Ken Holcomb

Inventor： Ken Holcomb

IPC: H05K1/09 ,  B32B38/04 ,  H05K3/46

CPC classification number: H05K3/4614 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0394 ,  H05K2201/10378 ,  H05K2203/061 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T156/1056

Abstract: The invention provides methods to mass laminate and interconnect high density interconnect circuit layers fabricated through parallel processing. Invention methods employ an inside-out interconnection strategy that eliminates plating of vias and provides defect-free outer circuit layers. Conductive paste and via layers are also key features of the invention.

Abstract translation: 本发明提供了通过并行处理制造的质量叠层和互连高密度互连电路层的方法。 本发明的方法采用内向外互连策略，其消除通孔的电镀并提供无缺陷的外部电路层。 导电浆料和通孔层也是本发明的关键特征。

公开(公告)号：US07791197B2

公开(公告)日：2010-09-07

申请号：US12068593

申请日：2008-02-08

Applicant: Daisuke Mizutani

Inventor： Daisuke Mizutani

IPC: H01L23/488

CPC classification number: H05K3/4007 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/10152 ,  H01L2224/13099 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/30105 ,  H05K1/113 ,  H05K3/423 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2203/0733 ,  Y10T29/49147 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a semiconductor element having a plurality of connection terminals, a circuit substrate electrically connected with the semiconductor element; and a connecting member arranged between the semiconductor element and the circuit substrate having a plurality of conductive projections each having a columnar portion, each of columnar portions are connected with each of connection terminals, a cross section of the columnar portion along a plane parallel to a surface of the semiconductor element being smaller than a surface area of each of connection terminals of the semiconductor element.

Abstract translation: 半导体器件具有具有多个连接端子的半导体元件，与半导体元件电连接的电路基板; 以及布置在所述半导体元件和所述电路基板之间的连接构件，所述连接构件具有多个具有柱状部分的导电突起，每个所述柱状部分与每个连接端子连接，所述柱状部分沿着平行于 半导体元件的表面小于半导体元件的每个连接端子的表面积。