公开(公告)号：US20160128183A1

公开(公告)日：2016-05-05

申请号：US14918618

申请日：2015-10-21

Applicant: KYOCERA Circuit Solutions, Inc.

Inventor： Keisaku MATSUMOTO

IPC: H05K1/02

CPC classification number: H05K1/0224 ,  H05K3/243 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/0347

Abstract: The wiring board of the present invention includes an insulating layer, a strip-shaped wiring conductor for signals disposed on a main surface of the insulating layer, and a plain conductor for grounding or power disposed on the main surface of the insulating layer; and the thickness of the plane conductor is larger than the thickness of the strip-shaped wiring conductor. In the wiring board of the present invention, the thickness of the plane conductor is preferably 1 to 15 μm larger than the thickness of the strip-shaped wiring conductor. The strip-shaped wiring conductor has a thickness of preferably 3 to 10 μm, and the plane conductor has a thickness of preferably 5 to 15 μm.

Abstract translation: 本发明的布线基板包括绝缘层，用于设置在绝缘层的主表面上的信号的带状布线导体和布置在绝缘层的主表面上的用于接地或电力的扁平导体; 并且平面导体的厚度大于带状布线导体的厚度。 在本发明的布线基板中，平面导体的厚度优选比带状布线导体的厚度大1〜15μm。 带状布线导体的厚度优选为3〜10μm，平面导体的厚度优选为5〜15μm。

公开(公告)号：US20150351257A1

公开(公告)日：2015-12-03

申请号：US14722246

申请日：2015-05-27

Applicant: KYOCERA Circuit Solutions, Inc.

Inventor： Kohichi OHSUMI ,  Kazuki OKA

IPC: H05K3/42 ,  H05K3/10 ,  H05K3/06 ,  H05K3/18

CPC classification number: H05K3/4644 ,  H05K3/108 ,  H05K2201/0347 ,  H05K2201/09336 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09681 ,  H05K2203/025 ,  H05K2203/0723 ,  H05K2203/1476

Abstract: A method for producing a wiring board includes the steps of forming an upper insulating layer on a lower insulating layer having a lower wiring conductor on its upper surface; forming a via-hole in the upper insulating layer; depositing a first base metal layer in the via-hole and on an upper surface of the upper insulating layer; forming a first plating resist layer on the first base metal layer; depositing a first electrolytically plated layer to completely fill at least the via-hole; forming a via conductor, and depositing a second base metal layer; forming a second plating resist layer on the second base metal layer; depositing a second electrolytically plated layer; and forming a wiring pattern.

Abstract translation: 制造布线板的方法包括以下步骤：在其上表面上形成具有下布线导体的下绝缘层上的上绝缘层; 在上绝缘层中形成通孔; 在所述通孔中和所述上绝缘层的上表面上沉积第一基底金属层; 在所述第一基底金属层上形成第一电镀抗蚀剂层; 沉积第一电解镀层以至少完全填充通孔; 形成通孔导体，并沉积第二基底金属层; 在所述第二基底金属层上形成第二电镀抗蚀剂层; 沉积第二电解镀层; 并形成布线图案。

公开(公告)号：US08982512B1

公开(公告)日：2015-03-17

申请号：US14037154

申请日：2013-09-25

Applicant: Magnecomp Corporation

Inventor： Christopher Schreiber ,  Christopher Gene Dunn

IPC: G11B5/48 ,  H05K1/02

CPC classification number: G11B5/48 ,  B33Y80/00 ,  G11B5/486 ,  H05K1/0215 ,  H05K1/0228 ,  H05K1/056 ,  H05K3/388 ,  H05K3/44 ,  H05K3/4685 ,  H05K2201/0347 ,  H05K2201/09554 ,  H05K2201/09827

Abstract: A low impedance, low crosstalk disk drive suspension circuit has multiple traces carrying a first polarity of a differential signal, interleaved with multiple traces carrying the second polarity of a differential signal. Each pair of conductors consisting of a trace of the first polarity and a trace of the second polarity may cross over each other at multiple crossover points. The crossover connections may utilize a second layer of copper trace conductors over the first and main layer, or alternatively the crossover connections may utilize an isolated portion of the suspension substrate.

Abstract translation: 低阻抗，低串扰磁盘驱动器悬架电路具有承载差分信号的第一极性的多个迹线，其交错具有携带差分信号的第二极性的多个迹线。 由第一极性的迹线和第二极性的迹线组成的每对导体可以在多个交叉点处彼此交叉。 交叉连接可以在第一层和主层上利用第二层铜迹线导体，或者交替连接可以利用悬浮基板的隔离部分。

公开(公告)号：US08809693B2

公开(公告)日：2014-08-19

申请号：US13362970

申请日：2012-01-31

Applicant: Daisuke Sakurai ,  Yoshihiko Yagi

Inventor： Daisuke Sakurai ,  Yoshihiko Yagi

IPC: H05K1/16 ,  H05K3/40 ,  H05K3/46 ,  H05K3/20 ,  H05K3/00

CPC classification number: H05K1/03 ,  H01L2224/16227 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0082 ,  H05K3/207 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4664 ,  H05K2201/0347 ,  H05K2203/0514 ,  H05K2203/056 ,  H05K2203/107 ,  Y10T29/49124

Abstract: A three-dimensional circuit board is formed by comprising a board, a first wiring-electrode group provided on a plurality of steps above the board, and a second wiring-electrode connected to the first wiring-electrode group at least in an altitude direction, in which at least a connecting portion between the first wiring-electrode group and the second wiring-electrode is integrated in a continuously identical shape.

Abstract translation: 三维电路板通过包括板，设置在板上方的多个台阶上的第一布线电极组和至少在高度方向连接到第一布线电极组的第二布线电极形成， 其中第一布线电极组和第二布线电极之间的至少一个连接部分被整合为连续相同的形状。

公开(公告)号：US08772647B1

公开(公告)日：2014-07-08

申请号：US13443508

申请日：2012-04-10

Applicant: Chien Te Chen

Inventor： Chien Te Chen

IPC: H01K3/10 ,  H05K1/11

CPC classification number: H05K1/113 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/0959 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Methods for the formation of single-cap VIPs in a substrate are described herein. The methods may include initially providing a substrate having a first and a second side, the first side being opposite of the second side. A via may then be constructed in the substrate, the via being formed within a via hole that extends from the first side to the second side of the substrate, the formed via having a first end located at the first side of the substrate, and a second end opposite the first end located at the second side of the substrate. A selective deposition may be performed of a conductive material on the second end of the via to form a conductive pad directly on the via on the second side of the substrate without depositing the conductive material onto the first side of the substrate.

Abstract translation: 本文描述了在底物中形成单帽VIP的方法。 所述方法可以包括最初提供具有第一和第二侧的衬底，第一侧与第二侧相对。 然后可以在衬底中构造通孔，所述通孔形成在从衬底的第一侧延伸到第二侧的通孔中，所形成的通孔具有位于衬底的第一侧的第一端，以及 第二端相对于位于基板的第二侧的第一端。 可以在通孔的第二端上执行导电材料的选择性沉积，以在衬底的第二侧上的通孔上直接形成导电焊盘，而不将导电材料沉积到衬底的第一侧上。

公开(公告)号：US20140185259A1

公开(公告)日：2014-07-03

申请号：US14097251

申请日：2013-12-05

Applicant: ZHEN DING TECHNOLOGY CO., LTD.

Inventor： YONG HA WOO ,  E-TUNG CHOU ,  WEN-LUN LO

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/00 ,  H05K1/09

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/09 ,  H01L2224/08238 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/15738 ,  H01L2924/181 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/0347 ,  H05K2201/0379 ,  H05K2201/09836 ,  H05K2201/10674 ,  H05K2203/0384 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts are larger than that of each of the first conductive posts.

Abstract translation: 封装基板包括电路板，多个第一导电柱和多个第二导电柱。 电路板包括形成在第一基底的第一表面上的第一基底和第一导电图案层。 第一导电柱从第一导电图案层延伸并电连接到第一导电图案层。 第二导电柱从第一导电图案层延伸并与之电连接。 每个第二导电柱的高度大于每个第一导电柱的高度。

公开(公告)号：US08646329B2

公开(公告)日：2014-02-11

申请号：US12747069

申请日：2008-12-04

Applicant: Erich Mattmann

Inventor： Erich Mattmann

IPC: G01F23/00

CPC classification number: H05K3/246 ,  B60K2015/03217 ,  G01D5/165 ,  G01F23/363 ,  G01F23/38 ,  H01C10/32 ,  H01H1/023 ,  H01H36/02 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/4061 ,  H05K2201/0338 ,  H05K2201/0347

Abstract: A tank sensor circuit board for a fill level sensor in a vehicle tank, including a support element, on which contact surfaces containing silver are applied using thick layer technology. The contact surfaces are made up of a silver layer and a top layer containing nickel, palladium and gold, completely or partly covering the silver layer.

Abstract translation: 一种用于车辆罐中的填充液位传感器的油箱传感器电路板，包括支撑元件，其上使用厚层技术施加包含银的接触表面。 接触表面由银层和包含镍，钯和金的顶层构成，完全或部分覆盖银层。

公开(公告)号：US08623751B2

公开(公告)日：2014-01-07

申请号：US13466514

申请日：2012-05-08

Applicant: Koichi Nakayama ,  Yoichi Hitomi ,  Takamasa Takano

Inventor： Koichi Nakayama ,  Yoichi Hitomi ,  Takamasa Takano

IPC: H01L21/02

CPC classification number: H01L23/147 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0557 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/423 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/0347 ,  H05K2201/09563 ,  H05K2201/09909 ,  H05K2203/1178 ,  H01L2224/05552

Abstract: A through-hole electrode substrate related to an embodiment of the present invention is arranged with a semiconductor substrate having a plurality of through-holes, an insulating layer formed with an insulating material on the inner walls of the plurality of through-holes and on at least one surface of the semiconductor substrate, a plurality of through-hole electrodes formed with a metal material inside the through-hole, and a plurality of gas discharge parts formed to contact with each of the plurality of through-hole electrodes which is exposed on at least one surface of the semiconductor substrate, the plurality of gas discharge parts externally discharges gas which is discharged from the inside of the plurality of through-hole electrodes.

Abstract translation: 与本发明的实施方式相关的贯通孔电极基板，配置有具有多个通孔的半导体基板，在多个贯通孔的内壁上形成有绝缘材料的绝缘层， 半导体衬底的至少一个表面，在通孔内部形成有金属材料的多个通孔电极，以及多个气体放电部分，形成为与暴露在多个通孔电极中的每一个通孔电极 半导体衬底的至少一个表面，多个气体放电部件从多个通孔电极的内部排出从外部排出的气体。

公开(公告)号：US08575496B2

公开(公告)日：2013-11-05

申请号：US13269079

申请日：2011-10-07

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K1/16 ,  H05K1/18

CPC classification number: H05K1/162 ,  H05K1/0269 ,  H05K1/112 ,  H05K3/205 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/09918 ,  H05K2203/166

Abstract: A multilayer printed wiring board including a layered capacitor section provided on a first interlayer resin insulation layer and a high dielectric layer and first and second layered electrodes that sandwich the high dielectric layer. A second interlayer resin insulation layer is provided on the first insulation layer and the capacitor section, and a metal thin-film layer is provided over the capacitor section and on the second insulation layer. An outermost interlayer resin insulation layer is provided on the second insulation layer and the metal thin-film layer. A mounting section is provided on the outermost insulation layer and has first and second external terminals to mount a semiconductor element. Multiple via conductors penetrate each insulation layer. The via conductors include first via conductors that electrically connect the first layered electrode to the first external terminals. Second via conductors electrically connect the second layered electrode to the second external terminals.

Abstract translation: 一种多层印刷线路板，包括设置在第一层间树脂绝缘层和高电介质层上的层状电容器部分和夹着高电介质层的第一和第二层状电极。 在第一绝缘层和电容器部分上设置第二层间树脂绝缘层，并且在电容器部分和第二绝缘层上设置金属薄膜层。 在第二绝缘层和金属薄膜层上设置最外层的层间树脂绝缘层。 安装部分设置在最外层绝缘层上，并且具有安装半导体元件的第一和第二外部端子。 多个通孔导体穿过每个绝缘层。 通孔导体包括将第一层状电极电连接到第一外部端子的第一通孔导体。 第二通孔导体将第二层状电极电连接到第二外部端子。

公开(公告)号：US20130219713A1

公开(公告)日：2013-08-29

申请号：US13663663

申请日：2012-10-30

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

IPC: H05K3/46

CPC classification number: H05K3/4644 ,  H05K3/24 ,  H05K3/4682 ,  H05K2201/0317 ,  H05K2201/0347 ,  H05K2203/072 ,  Y10T29/49155

Abstract: A method of manufacturing a laminate circuit board with a multilayer circuit structure which includes the steps of forming a metal layer on a substrate, patterning the metal layer to form a circuit metal layer, forming a nanometer plating layer on the circuit metal layer, forming a cover layer to cover the substrate and the nanometer plating layer, forming through holes in the cover layer to generate openings exposing part of the nanometer plating layer, and finally forming a second metal layer on the cover layer to fill up the openings is disclosed. The nanometer plating layer is used to obtain same effect of previously roughening by chemical bonding, such that no circuit width is reserved for compensation, and the density of the circuit increases such that much more dense circuit can be implemented.

Abstract translation: 一种制造具有多层电路结构的叠层电路板的方法，包括以下步骤：在基板上形成金属层，图案化金属层以形成电路金属层，在电路金属层上形成纳米电镀层，形成 盖层覆盖基板和纳米镀层，在盖层中形成孔，以产生露出纳米镀层的一部分的开口，最后在覆盖层上形成第二金属层以填充开口。 纳米电镀层用于通过化学键合获得与之前的粗糙化相同的效果，使得没有电路宽度被保留用于补偿，并且电路的密度增加，使得可以实现更加密集的电路。