公开(公告)号：US20240352287A1

公开(公告)日：2024-10-24

申请号：US18683425

申请日：2022-08-10

Applicant: Resonac Corporation

Inventor： Masashi OHKOSHI ,  Nozomu TAKANO ,  Kunihiko AKAI ,  Hiroyuki IZAWA ,  Yuka ITOH ,  Shunsuke TAKAGI

IPC: C09J9/02 ,  C09J179/08 ,  H05K1/11 ,  H05K3/46

CPC classification number: C09J9/02 ,  C09J179/08 ,  H05K1/113 ,  H05K3/46 ,  H05K2201/032 ,  H05K2201/0338 ,  H05K2203/0278 ,  H05K2203/1105

Abstract: A curable adhesive composition used for bonding a wiring member constituting a multilayered wiring board, in which the curable adhesive composition satisfies all the following conditions (A) and (B) when a thermal expansion coefficient and a glass transition temperature of a cured product are designated as CTE0 (ppm/° C.) and Tg0 (° C.), respectively:







(
A
)

⁢

5

≤

CTE
0

≤
270

⁢





(
B
)

⁢

140

≤

Tg
0

≤
280

公开(公告)号：US20240332644A1

公开(公告)日：2024-10-03

申请号：US18383130

申请日：2023-10-24

Applicant: SAMSUNG SDI CO., LTD.

Inventor： Jaepil AHN ,  Younghwan KWON ,  Hyeok LEE ,  Chuljung YUN

IPC: H01M10/42 ,  H01M50/209 ,  H01M50/284 ,  H05K1/14

CPC classification number: H01M10/425 ,  H01M50/209 ,  H01M50/284 ,  H05K1/144 ,  H01M2010/4278 ,  H05K2201/0338

Abstract: A battery pack, including a plurality of battery cells, and a state information transmission path for transmitting state information of the plurality of battery cells, wherein the state information transmission path includes a first circuit board unit including a first film layer and a first conductive layer formed over the first film layer, a second circuit board unit including a second film layer and a (2-1)th conductive layer and a (2-2)th conductive layer formed on different surfaces of the second film layer, and a conductive adhesive layer arranged between the first circuit board unit and the second circuit board unit to form an electrical connection therebetween.

公开(公告)号：US20240284591A1

公开(公告)日：2024-08-22

申请号：US18650918

申请日：2024-04-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tsuyoshi TAKAKURA ,  Masaaki MIZUSHIRO ,  Satoshi IZUMI ,  Ryuichiro WADA ,  Hiroki YOSHIMORI ,  Yoshihito OTSUBO ,  Tadashi NOMURA

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/0367 ,  H05K2201/0391

Abstract: A circuit module includes: a substrate including a first main surface and a second main surface; a resin layer on the first main surface of the substrate; an electronic component; a penetrating portion penetrating the resin layer in a thickness direction; a first conductor that is a pillar conductor present in the penetrating portion, the first conductor including a first bottom closer to the substrate and a second bottom inward of an outer surface of the resin layer; a second conductor that is a metal film covering at least a portion of a side surface of the first conductor, the second conductor including a portion extending continuously from the side surface of the first conductor to the same plane with the outer surface of the resin layer.

公开(公告)号：US20240260187A1

公开(公告)日：2024-08-01

申请号：US18423833

申请日：2024-01-26

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Hiroshi YOKOTA

IPC: H05K1/11 ,  H05K3/06 ,  H05K3/24

CPC classification number: H05K1/113 ,  H05K3/062 ,  H05K3/067 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/0347 ,  H05K2201/099

Abstract: A wiring board includes an insulating layer, first and second pads provided on the insulating layer and including a first surface in contact with the insulating layer, a second surface opposite to the first surface, and a side surface connecting the first and second surfaces, respectively, and a protective insulating layer provided above the insulating layer. The first and second pads have a portion exposed inside an opening in the protective insulating layer. The first pad has a portion opposing the second pad without the protective insulating layer interposed between the first and second pads. A region of the second surface of the first and second pads exposed from the protective insulating layer is covered with a plating layer. A region of the side surface of the first and second pads exposed from the protective insulating layer is exposed from the plating layer.

公开(公告)号：US20240215158A1

公开(公告)日：2024-06-27

申请号：US18209616

申请日：2023-06-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Mi Jeong JEON ,  Hyun Seok YANG ,  Tae Hee YOO ,  Chan Jin PARK

IPC: H05K1/03 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K1/0306 ,  H05K3/0017 ,  H05K3/4038 ,  H05K2201/0338 ,  H05K2203/0186 ,  H05K2203/0315 ,  H05K2203/0582 ,  H05K2203/072 ,  H05K2203/0723

Abstract: A printed circuit board includes a first insulating layer, a first metal layer disposed on the first insulating layer and including a first oxidation region on a side surface thereof, and a second metal layer disposed on the first metal layer. A method of manufacturing a printed circuit board includes forming a first metal layer on a first insulating layer, forming a second metal layer on a portion of the first metal layer, oxidizing another portion of the first metal layer to form a first oxidation region, and removing at least a portion of the first oxidation region.

公开(公告)号：US12022622B2

公开(公告)日：2024-06-25

申请号：US16166204

申请日：2018-10-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuki Takemori

IPC: H05K3/38 ,  H05K1/09 ,  H05K3/34 ,  H05K3/46 ,  H05K1/02 ,  H05K1/03 ,  H05K3/40

CPC classification number: H05K3/38 ,  H05K1/09 ,  H05K3/34 ,  H05K3/388 ,  H05K3/4644 ,  B32B2305/80 ,  B32B2457/08 ,  H05K1/0271 ,  H05K1/0306 ,  H05K3/4007 ,  H05K2201/0175 ,  H05K2201/0195 ,  H05K2201/0338

Abstract: A ceramic electronic component that includes an electronic component body having a superficial base ceramic layer and a surface electrode on a surface of the electronic component body. The surface electrode includes a first sintered layer on the base ceramic layer, a second sintered layer on the first sintered layer, and a plating layer on the second sintered layer. A peripheral section of the first sintered layer has an exposed surface which is not overlaid with the second sintered layer or the plating layer.

公开(公告)号：US20240206062A1

公开(公告)日：2024-06-20

申请号：US18565613

申请日：2022-06-27

Applicant: Lotte Energy Materials Corporation

Inventor： Chang Yol YANG ,  Won Jin BEOM ,  Hyung Cheol KIM ,  Kideok SONG

IPC: H05K1/09 ,  H05K3/06

CPC classification number: H05K1/09 ,  H05K3/062 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/0355 ,  H05K2203/0323 ,  H05K2203/0353 ,  H05K2203/0384

Abstract: Disclosed are an ultra-thin copper foil with a carrier foil and a method for manufacturing an embedded substrate by using the same, the ultra-thin copper foil with a carrier foil including: a carrier foil; a non-etching release layer on the carrier foil; a first ultra-thin copper foil layer on the non-etching release layer; an etch stop layer on the first ultra-thin copper foil layer; and a second ultra-thin copper foil layer on the etch stop layer.

公开(公告)号：US20240188217A1

公开(公告)日：2024-06-06

申请号：US18439530

申请日：2024-02-12

Applicant: TTM TECHNOLOGIES INC.

Inventor： Matthew Douglas Neely ,  John Joseph Konrad ,  James Gilbert McKay ,  Caleb Lathan Griffie

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/18 ,  H05K3/42

CPC classification number: H05K1/116 ,  H05K3/0047 ,  H05K3/18 ,  H05K3/423 ,  H05K3/429 ,  H05K2201/0338 ,  H05K2201/09845 ,  H05K2203/0723

Abstract: A multilayer structure for a printed wiring board (PWB) includes a plurality of insulating layers interleaved with a plurality of conductive layers including one or more inner conductive layers, a top conductive layer, and a bottom conductive layer. The multilayer structure also includes at least one through-hole through the plurality of insulating layers and the plurality of conductive layers. The multilayer structure also includes at least one secondary material layer formed on at least one inner conductive trace or a terminating land having a surface and an edge near one of the at least one through-hole, the at least one secondary material layer after being removed partially defining a recess that allows plating on both the edge and the surface of the at least one inner conductive trace or the terminating land. The at least one through-hole includes a first plated segment seamless connected to a second plated segment wrapped over the edge of the at least one inner conductive trace or terminating land and extending at least a portion of the surface of the at least one inner conductive trace or terminating land.

公开(公告)号：US20240171839A1

公开(公告)日：2024-05-23

申请号：US18428017

申请日：2024-01-31

Applicant: LG INNOTEK CO., LTD.

Inventor： Hae Sik KIM ,  So Hee CHOI ,  Jee Heum PAIK ,  Na Kyung KWON

IPC: H04N23/54 ,  H04N23/57 ,  H05K1/18

CPC classification number: H04N23/54 ,  H04N23/57 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/0338 ,  H05K2201/09409 ,  H05K2201/10121 ,  H05K2201/10151 ,  H05K2201/10969

Abstract: A circuit board includes an insulating portion and a pattern portion on the insulating portion. The insulating portion includes a first insulating region and a second insulating region outside the first insulating region and spaced apart from the first insulating region with a separation region therebetween. The pattern portion includes a first pattern portion for signal transmission and a second pattern portion including a dummy pattern separated from the first pattern portion. The first pattern portion includes a first terminal portion on the first insulating region, a second terminal portion on the second insulating region, and a connection portion on the separation region and connecting between the first terminal portion and the second terminal portion. The second pattern portion includes a second-first pattern portion on the first insulating region and a second-second pattern portion on the second insulating region and separated from the second-first pattern portion.

公开(公告)号：US11871525B2

公开(公告)日：2024-01-09

申请号：US17439494

申请日：2019-12-17

Applicant: KYOCERA Corporation

Inventor： Yoshihiro Hasegawa

IPC: H05K1/03 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K3/4661 ,  H05K1/0373 ,  H05K1/116 ,  H05K2201/0209 ,  H05K2201/0338

Abstract: A wiring board according to the present disclosure has at least a structure in which a wiring conductor layer is layered on a surface of an insulating layer containing particles of silica, and some particles of silica among the particles of silica contained in the insulating layer are partially exposed on the surface of the insulating layer. The wiring conductor layer includes a seed layer in contact with the insulating layer and a plated conductor layer formed on a surface of the seed layer. At a contact surface between the exposed portions of the particles of silica and the seed layer, an amorphous layer of silica derived from the particles of silica and an amorphous layer of metal derived from metal forming the seed layer are present.