公开(公告)号：US20250107130A1

公开(公告)日：2025-03-27

申请号：US18976256

申请日：2024-12-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Po-Wen Su ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L21/311 ,  H01L29/20 ,  H01L29/66

Abstract: A semiconductor structure includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a first passivation layer on the insulating layer, a contact structure disposed on the first passivation layer and extending through the first passivation layer to directly contact a portion of the barrier layer, and an insulating layer interposed between the barrier layer and the first passivation layer and comprising an extending portion protruding toward a bottom corner of the contact structure.

公开(公告)号：US20250107114A1

公开(公告)日：2025-03-27

申请号：US18380641

申请日：2023-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Tseng Chen ,  Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L29/94 ,  H01L29/06

Abstract: The invention provides a metal oxide semiconductor (MOS) capacitor structure, which includes a counter-doping region in the channel region directly below the gate. Between the deep ion well and the counter-doping region is a semiconductor region. The doping concentration of the semiconductor region is lower than that of the deep ion well. The P-type well ion implantation processes in the active region of the device can be omitted, so the production cost is lower, and the dosage of the counter-doping region can be reduced, which improves the time-dependent dielectric collapse (TDDB) issue.

公开(公告)号：US12262645B2

公开(公告)日：2025-03-25

申请号：US18224066

申请日：2023-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

公开(公告)号：US12261086B2

公开(公告)日：2025-03-25

申请号：US17586699

申请日：2022-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Chin-Hung Chen

IPC: H01L21/8234 ,  H01L23/60 ,  H01L27/088

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

公开(公告)号：US12261083B2

公开(公告)日：2025-03-25

申请号：US17740377

申请日：2022-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Sun

IPC: H01L21/768 ,  H01L23/522

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an active device having a gate structure and a source/drain region on a substrate, forming an interlayer dielectric (ILD) layer on the active device, removing part of the ILD layer to form a contact hole on the active device without exposing the active device and the bottom surface of the contact hole is higher than a top surface of the gate structure, and then forming a metal layer in the contact holt to form a floating contact plug.

公开(公告)号：US12261052B2

公开(公告)日：2025-03-25

申请号：US18608940

申请日：2024-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Kun-Yuan Liao ,  Lung-En Kuo ,  Chih-Tung Yeh

IPC: H10D30/01 ,  H01L21/306 ,  H01L21/308 ,  H10D30/47 ,  H10D62/824 ,  H10D62/85

Abstract: A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.

公开(公告)号：US20250098209A1

公开(公告)日：2025-03-20

申请号：US18383055

申请日：2023-10-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung LI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate; a first well region disposed in the substrate and with a first electrical property; a second well region with the first electrical property disposed in the substrate and separated from the first well region; a first gate dielectric layer disposed on the first well region and having a first thickness; a second gate dielectric layer, disposed on the second well region, separated from the first gate dielectric layer and having a second thickness less than the first thickness; a first gate electrode disposed on the first gate dielectric layer; a second gate electrode disposed on the second gate dielectric layer and separated from the first gate electrode; a drain region disposed in the first well region; and a source region disposed in the second well region.

公开(公告)号：US20250096000A1

公开(公告)日：2025-03-20

申请号：US18487141

申请日：2023-10-16

Applicant: United Microelectronics Corp.

Inventor： Kun-Ju Li ,  Hsin-Jung Liu ,  Jhih Yuan Chen ,  I-Ming Lai ,  Ang Chan ,  Wei Xin Gao ,  Hsiang Chi Chien ,  Hao-Che Hsu ,  Chau Chung Hou ,  Zong Sian Wu

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/762

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.

公开(公告)号：US20250095722A1

公开(公告)日：2025-03-20

申请号：US18969210

申请日：2024-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hsiu Wu ,  Tsung-Hsun Wu

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094

Abstract: A random access memory, including a first gate crossing over a first doped region to constitute a write transistor, a second gate crossing over a second doped region to constitute a first read transistor, a third gate crossing over the first doped region and the second doped region to constitute a second read transistor, a metal bridge electrically connected to the second gate and the third gate, and a junction of the first source, the second gate and the third gate is a storage node.

公开(公告)号：US20250089448A1

公开(公告)日：2025-03-13

申请号：US18381646

申请日：2023-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Jin-Yan Chiou ,  Hsiang-Wen Ke

IPC: H10K50/81 ,  H10K50/11 ,  H10K50/82 ,  H10K50/856 ,  H10K59/131

Abstract: An organic light-emitting diode display device includes a first light-emitting layer, a first anode, a first reflective pattern, and a dielectric material. The first light-emitting layer, the first anode, and the first reflective pattern are located in a first sub-pixel region. The first anode is disposed under the first light-emitting layer in a vertical direction, and the first reflective pattern is disposed under the first anode in the vertical direction. The dielectric material is partly disposed between the first anode and the first reflective pattern, and the first reflective pattern is electrically connected with the first anode.