公开(公告)号：US20140021601A1

公开(公告)日：2014-01-23

申请号：US13644749

申请日：2012-10-04

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  Shih-Chieh Chang ,  Chia-Yeh Huang ,  Chin-Tang Hsieh

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L21/76885 ,  H01L21/4853 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.

公开(公告)号：US20030008529A1

公开(公告)日：2003-01-09

申请号：US10103971

申请日：2002-03-25

Applicant: Chipbond Technology Corporation

Inventor： Lu-Chen Hwan ,  Dang-Cheng Yiu

IPC: H01L021/66 ,  H01L021/301

CPC classification number: H01L21/78 ,  B23K26/3576 ,  Y10S438/964 ,  Y10S438/974 ,  Y10T428/31

Abstract: A laser sintering system is provided for sintering a die having a serrate edge. The laser sintering system comprises a laser generator for generating a laser beam and a movable carriage for carrying said die. The laser beam sinters the serrate edge of said die into a smooth edge. A method of sintering a die, the die having a serrate edge, comprises the following steps of providing a die and using a laser beam sintering the serrate edge of said die into a smooth edge. A die has a smooth edge sintered by a laser beam.

Abstract translation: 提供了一种用于烧结具有锯齿边缘的模具的激光烧结系统。 激光烧结系统包括用于产生激光束的激光发生器和用于承载所述管芯的可移动托架。 激光束将所述模具的锯齿边缘烧结成平滑的边缘。 一种烧结模具的方法，具有锯齿边缘的模具包括以下步骤：提供模具并使用将所述模具的锯齿边缘烧结成光滑边缘的激光束。 模具具有通过激光束烧结的光滑边缘。

公开(公告)号：US20250038130A1

公开(公告)日：2025-01-30

申请号：US18771070

申请日：2024-07-12

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Sheng-Han Yang ,  Shih-Chieh Chang

IPC: H01L23/00 ,  H01L23/58

Abstract: A wafer includes chips, a scribe lane, a metal layer and an inhibitor made of a nonconductive material. The metal layer is provided on the scribe lane and the chip located next to the scribe lane. The inhibitor covers the scribe lane and the chip next to the scribe line and includes a first removed part and an inhibition part which are located above a second removed part and a residual part of the metal layer, respectively. The scribe lane, the first and second removed parts are removed, and the inhibition part and the residual part are retained on each of the chips after a wafer cutting process. The inhibitor is provided to prevent the residual part of the metal layer from being lifted up or generating a metal burr during the wafer cutting process.

公开(公告)号：US20230380053A1

公开(公告)日：2023-11-23

申请号：US18134082

申请日：2023-04-13

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chun-Te Lee ,  Chih-Ming Peng ,  Pi-Yu Peng ,  Hui-Yu Huang

IPC: H05K1/02 ,  H01L21/60 ,  H05K3/00 ,  H05K1/03

CPC classification number: H05K1/0266 ,  H01L21/60 ,  H05K3/0044 ,  H05K1/03 ,  H01L2021/60022 ,  H05K2201/10893

Abstract: A flip-chip bonding structure includes a chip and a circuit board, the chip is bonded to the circuit board by bumps. The circuit board includes a light-transmissive substrate, a first circuit group, a second circuit group, a boundary circuit and an identifying member. The boundary circuit is located between the first and second circuit groups and projects a boundary circuit shadow on light-transmissive substrate. The boundary circuit shadow can be recognized according to the identifying member and is provided to identify the boundary between the first and second circuit groups or identify the position of leads with the smallest pitch.

公开(公告)号：US11792923B2

公开(公告)日：2023-10-17

申请号：US17470038

申请日：2021-09-09

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Shih-Chieh Chang ,  Hui-Yu Huang ,  Chih-Ming Peng ,  Chun-Te Lee

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/14

CPC classification number: H05K1/0277 ,  H05K1/14 ,  H05K1/189 ,  H05K2201/09036

Abstract: A storage device of the present invention is provided to store flexible circuit packages, each of the flexible circuit packages includes an electronic component and two circuit portions warped at both sides of the electronic component, respectively. The storage device includes a first carrier and a second carrier. The first carrier includes first accommodation elements provided for placement of the flexible circuit packages, and the second carrier includes a first press portion and a second press portion. As the second carrier is placed on the first carrier, the first and second press portions are provided to press the two circuit portions warped upwardly toward the second carrier so as to reduce the warpage of the two circuit portions.

公开(公告)号：US20230326896A1

公开(公告)日：2023-10-12

申请号：US18108733

申请日：2023-02-13

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Sheng-Jen Wu ,  Shih-Chung Chang ,  Hsueh-Shun Yeh ,  Chun-Te Lee

IPC: H01L23/00

CPC classification number: H01L24/26 ,  H01L24/32 ,  H01L24/29 ,  H01L24/05 ,  H01L2224/26125 ,  H01L2224/04026 ,  H01L2224/05558 ,  H01L2224/05573 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2924/0132 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05644 ,  H01L2224/05672 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29109 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/29017 ,  H01L2224/29019 ,  H01L2224/29034 ,  H01L2224/32225

Abstract: A COF package includes a substrate and a chip, composite bumps on the chip are bonded to leads on the substrate. Each of the composite bumps includes a raising strip, a UBM layer and a bonding layer. A bonding rib is formed on the bonding layer because of the raising strip and the UBM layer, and the bonding rib on each of the composite bumps can be inserted into each of the leads and surface-contact with each of the leads to increase weld length and bonding strength between the bonding layer and the leads and further reduce a force required for bonding the chip to the substrate in a flip-chip bonding process.

公开(公告)号：US11764090B2

公开(公告)日：2023-09-19

申请号：US17690121

申请日：2022-03-09

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Hsu-Chi Lee ,  Pi-Yu Peng ,  Chun-Te Lee

IPC: H01L21/673

CPC classification number: H01L21/67333

Abstract: A tray includes a body for placement of a component (e.g. electronic component) and a taker disposed on a bottom surface of the body. The taker is used to take a spacer and includes a first taking element and a second taking element. The first taking element includes a first connection portion and a first confinement portion, and the second taking element includes a second connection portion and a second confinement portion. An accommodation space is provided between the first and second connection portions and a passageway is provided between the first and second confinement portions. While the spacer is moved through the passageway and into the accommodation space, it is confined in the accommodation space by the first and second confinement portions such that the taker can take away the spacer to show another tray located under the spacer as the tray is removed.

公开(公告)号：US20230170301A1

公开(公告)日：2023-06-01

申请号：US17972648

申请日：2022-10-25

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Chun-Ting Kuo ,  Lung-Hua Ho ,  Chih-Ming Kuo

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/552

CPC classification number: H01L23/5286 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/552

Abstract: A semiconductor structure includes a substrate, a dielectric layer, a connection layer and wire layers. The dielectric layer is disposed on a surface of the substrate and includes vias showing the surface. The connection layer is disposed on the dielectric layer, a first connection portion of the connection layer is located in the vias and connected to the surface, a second connection portion of the connection layer is connected to the dielectric layer. A first ground portion of the ground metal layer is connected to the first connection portion of the connection layer, and a second ground portion of the ground metal layer is connected to the second connection portion of the connection layer. Each of the wire layers is disposed on the second connection portion of the connection layer, and the second ground portion is located between the adjacent wire layers.

公开(公告)号：US11522517B2

公开(公告)日：2022-12-06

申请号：US16581901

申请日：2019-09-25

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Cheng-Fan Lin

IPC: H03H9/02 ,  H01L41/047 ,  H03H9/05 ,  H03H9/145

Abstract: A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.

公开(公告)号：US11350518B2

公开(公告)日：2022-05-31

申请号：US16927059

申请日：2020-07-13

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chia-Sung Lin ,  Huan-Kai Chou ,  Chia-Hsin Yen ,  Wen-Fu Chou

IPC: H05K3/30 ,  H05K1/02 ,  H05K13/04

Abstract: In a method of heat sink attachment, a heat-sink tape includes a plurality of heat sinks and a flexible carrier, and a holder is provided to allow the heat sinks on the moving heat-sink tape to peel from the flexible carrier and attach to a heat-sink mounting area of a moving circuit tape automatically and successively.