公开(公告)号：US09954431B2

公开(公告)日：2018-04-24

申请号：US14901482

申请日：2014-05-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Nan Zhang

IPC: H02M1/36 ,  H02M1/00

CPC classification number: H02M1/36 ,  H02M2001/0006

Abstract: A starting circuit (10) of a power management chip, comprising: a starting capacitor (C3) which is used for connecting a power supply via an external resistor (R2) to perform charging; a switch circuit (100) which is connected between the external resistor (R2) and the starting capacitor (C3); a voltage detection circuit (200) which is used for detecting a voltage on the starting capacitor (C3) and is connected to the switch circuit (100) so as to control the on/off switching of the switch circuit (100); and a voltage maintaining circuit (300) which is connected between the starting capacitor (C3) and an operating circuit of the power management chip and is used for acquiring a voltage that maintains the starting capacitor (C3) from the operating circuit of the power management chip, wherein when the voltage detection circuit (200) detects that the starting capacitor (C3) reaches the starting voltage of the power management chip, the broken circuit of the switch circuit (100) is controlled. Further provided is a power management chip including the above-mentioned starting circuit (10). Disconnecting an external power source from the starting capacitor after the operating circuit of the power management chip is started can reduce the electric energy consumption.

公开(公告)号：US09903884B2

公开(公告)日：2018-02-27

申请号：US14435925

申请日：2013-08-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Meihan Guo ,  Xinwei Zhang ,  Changfeng Xia ,  Wei Su

IPC: G01P15/125 ,  H02N1/08 ,  B81B7/02

CPC classification number: G01P15/125 ,  B81B7/02 ,  G01P2015/0837 ,  H01G5/16 ,  H02N1/08

Abstract: A parallel plate capacitor includes a first polar plate (10), and a second polar plate disposed opposite to the first polar plate (10). The parallel plate capacitor further includes at least a pair of sensitive units disposed on a substrate forming the first polar plate (10); the sensitive units includes sensitive elements (21a, 21b, 22a, 22b) and element connecting arms (23a, 23b, 24a, 24b) connecting the sensitive elements (21a, 21b, 22a, 22b) to the first polar plate (10). The parallel plate capacitor further includes anchoring bases (30, 31, 32, 33) disposed on a substrate where the second polar plate is located; the anchoring bases (30, 31, 32, 33) are connected to the element connecting arms (23a, 23b, 24a, 24b) via cantilever beams (30a, 30b, 31a, 31b, 32a, 32b, 33a, 33b); each element connecting arm (23a, 23b, 24a, 24b) is connected to at least two anchoring bases (30, 31, 32, 33), which are symmetric with respect to the element connecting arm. The parallel plate capacitor is more likely to be influenced by an external factor, thus being more likely to experience capacitance change. An acceleration sensor including the parallel plate capacitor is also provided.

公开(公告)号：US09865702B2

公开(公告)日：2018-01-09

申请号：US15541155

申请日：2015-09-28

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Feng Huang ,  Guangtao Han ,  Guipeng Sun ,  Feng Lin ,  Longjie Zhao ,  Huatang Lin ,  Bing Zhao ,  Lixiang Liu ,  Liangliang Ping ,  Fengying Chen

IPC: H01L29/66 ,  H01L29/739 ,  H01L21/02 ,  H01L21/311 ,  H01L21/265 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/66325 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/26513 ,  H01L21/31116 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7393 ,  H01L29/78

Abstract: The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching and injecting N-type ions between the mini oxide layer (60) and the STI (40) adjacent to the mini oxide layer (60) to form a drain electrode, and at the same time forming a source electrode (51) inside the second P well (34).

公开(公告)号：US20170352722A1

公开(公告)日：2017-12-07

申请号：US15539554

申请日：2016-09-10

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong ZHONG ,  Xiaoshe DENG ,  Dongfei ZHOU

IPC: H01L29/06 ,  H01L29/861 ,  H01L21/768 ,  H01L21/02 ,  H01L21/04 ,  H02M3/158 ,  H01L21/78

Abstract: A semiconductor rectifying device and a method of manufacturing the same. The semiconductor rectifying device includes: a substrate of a first conductivity type (100), an epitaxial layer of a first conductivity type (200) formed on the substrate of the first conductivity type (100), wherein the epitaxial layer of the first conductivity type (200) defines a plurality of trenches (310) thereon; a filling structure (300) comprising an insulating material formed on the inner surface of the trench (310) and a conductive material filled in the trench (310); a doped region of a second conductivity type (400) formed in the surface of the epitaxial layer of the first conductivity type (200) located between the filling structures (300); an upper electrode (600) formed on a surface of the epitaxial layer of the first conductivity type (200); a guard ring (700) formed in the surface layer of the epitaxial layer of the first conductivity type (200); and a guard layer (800).

公开(公告)号：US09837532B2

公开(公告)日：2017-12-05

申请号：US15119868

申请日：2015-05-04

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangsheng Zhang ,  Sen Zhang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A laterally diffused metal oxide semiconductor device includes: a substrate (10); a buried layer region (32) in the substrate; a well region (34) on the buried layer region (32); a gate region on the well region; a source region (41) and a drain region (43) which are located at two sides of the gate region; and a super junction structure. The source region (41) is located in the well region (34); the drain region (34) is located in the super junction structure; the gate region comprises a gate oxide layer and a gate electrode on the gate oxide layer; and the super junction structure comprises a plurality of N-columns and P-columns, wherein the N-columns and the P-columns are alternately arranged in a direction which is horizontal and is perpendicular to the direction of a connecting line between the source region and the drain region, each N-column comprises a top-layer N-region (23) and a bottom-layer N-region which are butted vertically, and each P-column comprises a top-layer P-region (24) and a bottom-layer P-region which are butted vertically.

公开(公告)号：US09812334B2

公开(公告)日：2017-11-07

申请号：US14436037

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Qiliang Sun

IPC: H01L21/311 ,  B81C1/00

CPC classification number: H01L21/31116 ,  B81C1/00476 ,  B81C2201/0132

Abstract: A corrosion method of a passivation layer (320) of a silicon wafer (300) includes: pouring hydrofluoric acid solution (100) into a container (200) with an open top; putting the silicon wafer (300) to the opening of the container (200) and one side of the silicon wafer (300) with the passivation layer (320) is opposite to the hydrofluoric acid solution (100); the hydrogen fluoride gas generated from the volatilization of the hydrofluoric acid solution (100) corrodes the passivation layer (320) of the silicon wafer (300), the corrosion time is larger or equal to (thickness of the passivation layer/corrosion rate). By means of the corrosion of the passivation layer of silicon wafer by the fluoride gas generated from the volatilization of the hydrofluoric acid solution, the fluoride gas can fully touch the passivation layer; therefore the passivation layer can be completely corroded, and the corrosion precision is high.

公开(公告)号：US09768292B2

公开(公告)日：2017-09-19

申请号：US14891470

申请日：2014-05-16

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shu Zhang ,  Guangtao Han ,  Guipeng Sun

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/02 ,  H01L21/027 ,  H01L21/28 ,  H01L21/426

CPC classification number: H01L29/7816 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0274 ,  H01L21/28035 ,  H01L21/426 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S210); coating a photoresist on the surface of the wafer (S220); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (S230); performing ion implantation via the first implantation window to form a drift region in the substrate (S240); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (S250); performing photoetching by using the photoetching mask of the oxide layer of the drift region (S260); and etching the oxide layer to form the oxide layer of the drift region (S270). Further provided is a laterally diffused metal oxide semiconductor device.

公开(公告)号：US09685386B2

公开(公告)日：2017-06-20

申请号：US14403565

申请日：2013-09-04

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Xiaodong He

IPC: H01L23/552 ,  H01L21/66 ,  H01L29/78 ,  H01L23/522

CPC classification number: H01L22/34 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/552 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor test structure for MOSFET noise testing. The semiconductor test structure includes: a MOSFET device having a first conductivity type formed on a first well region of a semiconductor substrate; a metal shielding layer formed on the MOSFET device, the metal shielding layer completely covering the MOSFET device and extending beyond the circumference of the first well region; a deep well region having a second conductivity type formed in the semiconductor substrate close to the bottom surface of the first well region, the deep well region extending beyond the circumference of the first well region; wherein a vertical via is formed between the portion of the metal shielding layer extending beyond the first well region and the portion of the deep well region extending beyond the first well region to couple the metal shielding layer to the deep well region. The metal shielding layer is used to be connected to the ground terminal of a testing machine during testing, and the first conductivity type and the second conductivity type are opposite conductivity types.

公开(公告)号：US20170011144A1

公开(公告)日：2017-01-12

申请号：US15119249

申请日：2015-05-08

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Yifeng HU ,  Xiaodong HE ,  Xinxin LIU

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/78 ,  H01L27/0207 ,  Y02E60/76 ,  Y04S40/22

Abstract: A high-voltage device simulation model and a modeling method thereof are provided. The simulation model comprises: a core transistor (101), a drain terminal resistor (102) and a source terminal resistor (103), wherein a first terminal of the drain terminal resistor (102) is electrically connected to a drain (d1) of the core transistor (101) and a second terminal of the drain terminal resistor (102) serves as the drain of the high voltage device; a first terminal of the source terminal resistor (103) is electrically connected to a source (s1) of the core transistor (101) and a second terminal of the source terminal resistor (103) serves as the source of the high voltage device. The relations of the resistance value of the drain terminal resistor (102) are as follows: RD=(RD0/W)*(1+CRD*VDERDD+1/(1+PRWDD*VDERDD))*TFAC_RD, and TFAC_RD=(1+TCRD1*(TEMP−25)+TCRD2*(TEMP−25)*(TEMP−25)).

Abstract translation: 提供了一种高压器件仿真模型及其建模方法。 模拟模型包括：芯体晶体管（101），漏极端子电阻（102）和源极端子电阻（103），其中漏极端子电阻（102）的第一端电连接到漏极（d1）的漏极 芯极晶体管（101）和漏极端子电阻（102）的第二端子用作高压器件的漏极; 源极端子电阻器（103）的第一端子电连接到核心晶体管（101）的源极（s1），源极端子电阻器（103）的第二端子用作高压器件的源极。 漏极端子电阻（102）的电阻值的关系如下：RD =（RD0 / W）*（1 + CRD * VDERDD + 1 /（1 + PRWDD * VDERDD））* TFAC_RD和TFAC_RD = 1 + TCRD1 *（TEMP-25）+ TCRD2 *（TEMP-25）*（TEMP-25））。

公开(公告)号：US20160380071A1

公开(公告)日：2016-12-29

申请号：US14902516

申请日：2014-07-29

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Xiaoshe DENG ,  Qiang RUI ,  Shuo ZHANG ,  Genyi WANG

IPC: H01L29/66 ,  H01L29/739 ,  H01L21/265 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L29/66333 ,  H01L21/26513 ,  H01L21/31111 ,  H01L29/0611 ,  H01L29/7395

Abstract: An insulated gate bipolar transistor (IGBT) manufacturing method comprises the following steps: providing a semiconductor substrate of a first conducting type, the semiconductor substrate having a first major surface and a second major surface (100); forming a field-stop layer of a second conducting type on the first major surface of the semiconductor substrate (200); growing an oxide layer on the field-stop layer (300); removing the oxide layer from the field-stop layer (400); forming an epitaxial layer on the field-stop layer from which the oxide layer has been removed; and then manufacturing an IGBT on the epitaxial layer (600). Before regular manufacturing of an IGBT, the surface defects of a substrate material are eliminated as many as possible before epitaxy is formed, and the quality of an epitaxial layer is improved, thereby improving the quality of the whole IGBT.

Abstract translation: 一种绝缘栅双极晶体管（IGBT）制造方法，包括以下步骤：提供第一导电类型的半导体衬底，该半导体衬底具有第一主表面和第二主表面（100）; 在半导体衬底（200）的第一主表面上形成第二导电类型的场阻止层; 在所述场 - 停止层（300）上生长氧化物层; 从所述场停止层（400）去除所述氧化物层; 在去除了氧化物层的场 - 停止层上形成外延层; 然后在外延层（600）上制造IGBT。 在正常制造IGBT之前，在形成外延之前尽可能地消除基板材料的表面缺陷，提高外延层的质量，从而提高整个IGBT的质量。