中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

82 records (took 0.029 seconds)

    SEMICONDUCTOR DEVICE
    22.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20080054379A1

    公开(公告)日：2008-03-06

    申请号：US11675476

    申请日：2007-02-15

    Applicant: Yoji Nishio ,  Yutaka Uematsu ,  Hideki Osaka ,  Tsutomu Hara ,  Seiji Funaba

    Inventor： Yoji Nishio ,  Yutaka Uematsu ,  Hideki Osaka ,  Tsutomu Hara ,  Seiji Funaba

    IPC: H01L29/94

    CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C7/109

    Abstract: Input circuit ensuring a noise margin for a reference voltage. A semiconductor chip 11a comprises a pad 14 that inputs a reference voltage Vref, an input circuit 13, a resistance element R1 connected between an input terminal of the input circuit 13 and the pad 14, a capacitance element C1 connected between the input terminal of the input circuit 13 and a power supply VDD, and a capacitance element C2 connected between the input terminal of the input circuit 13 and a ground VSS within the semiconductor chip. A resistance value of the resistance element R1 is set based on an impedance characteristic of a network, for supplying the reference voltage Vref.

    Abstract translation: 输入电路确保参考电压的噪声容限。 半导体芯片11a包括输入参考电压Vref的焊盘14，连接在输入电路13的输入端子和焊盘14之间的电阻元件R 1，连接在输入端13之间的电容元件C 1 输入电路13的端子和电源VDD，以及连接在输入电路13的输入端子和半导体芯片内的接地VSS之间的电容元件C 2。 基于网络的阻抗特性来设定电阻元件R 1的电阻值，用于提供基准电压Vref。

    Main board for backplane buses
    24.
    发明申请
    Main board for backplane buses 失效
    背板总线主板

    公开(公告)号：US20060232949A1

    公开(公告)日：2006-10-19

    申请号：US11404912

    申请日：2006-04-17

    Applicant: Hideki Osaka

    Inventor： Hideki Osaka

    IPC: H05K7/06

    CPC classification number: H05K1/0236 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/167 ,  H05K2201/044 ,  H05K2201/09681 ,  H05K2201/0969

    Abstract: A motherboard for backplane buses is provided that reduces noise due to entry of external signals into signal wiring which interconnects modules, or noise due to any external signals entering a power supply after being routed around the power supply. An EBG pattern formed up of two wiring regions different from each other in impedance is periodically disposed in at least three arrays as part of the power supply layer(s) constituting a microstripline structure (one layer adjacent to a signal layer is a power supply layer, and the other layer-is interposed in air) or a stripline structure (both layers adjacent to a signal layer are power supply layers); the part of the power supply layer(s) not being involved in signal transmission between the modules on the motherboard for backplane buses.

    Abstract translation: 提供了用于背板总线的主板，其将由于外部信号进入到互连模块的信号布线而引起的噪声，或者由于任何外部信号在绕过电源而进入电源之后产生的噪声。 由构成微带结构的电源层的一部分（至少与信号层相邻的一层是供电层），在至少三个阵列中周期性地设置由阻抗彼此不同的两个布线区域形成的EBG图案 ，另一层插入空气中）或带状线结构（与信号层相邻的两层是电源层）; 电源层的一部分不涉及用于背板总线的主板上的模块之间的信号传输。

    Printed board inspecting apparatus
    26.
    发明授权
    Printed board inspecting apparatus 失效
    印刷板检测仪器

    公开(公告)号：US06924651B2

    公开(公告)日：2005-08-02

    申请号：US10212209

    申请日：2002-08-06

    Applicant: Hideki Osaka ,  Toyohiko Komatsu

    Inventor： Hideki Osaka ,  Toyohiko Komatsu

    IPC: G01R31/02 ,  G01R5/00 ,  G01R31/11 ,  G01R31/28 ,  G01R27/28 ,  G01R31/00

    CPC classification number: G01R31/11 ,  G01R31/2806 ,  Y10T29/49004 ,  Y10T29/4913

    Abstract: A printed board inspecting apparatus includes: an input unit for inputting a pulse from a first signal line; a receiving unit for receiving a voltage induced in a second signal line in response to the input pulse inputted; and a judging unit for judging whether or not a ratio between a voltage of the input pulse and the voltage induced in the second signal line is within a predetermined range. A check is made using a TDR method to determine whether or not the degree of coupling is within a range of specified values and a check is made to determine each of the voltage of the polarized RZ signal and the pulse width time is within a range of specified values to thereby inspect a printed board and a semiconductor chip constituting a bus using a directional coupler.

    Abstract translation: 印刷电路板检查装置包括：输入单元，用于输入来自第一信号线的脉冲; 接收单元，用于响应输入的输入脉冲接收在第二信号线中感应的电压; 以及判断单元，用于判断输入脉冲的电压与第二信号线中感应的电压之间的比率是否在预定范围内。 使用TDR方法进行检查，以确定耦合度是否在指定值的范围内，并且进行检查以确定极化RZ信号的每个电压，并且脉冲宽度时间在 从而使用定向耦合器检查构成总线的印刷电路板和半导体芯片。

    Design support apparatus for circuit including directional coupler, design support tool, method of designing circuit, and circuit board
    27.
    发明授权
    Design support apparatus for circuit including directional coupler, design support tool, method of designing circuit, and circuit board 失效
    包括定向耦合器，设计支持工具，电路设计方法和电路板在内的电路设计支持设备

    公开(公告)号：US06829749B2

    公开(公告)日：2004-12-07

    申请号：US10214126

    申请日：2002-08-08

    Applicant: Hideki Osaka ,  Toyohiko Komatsu

    Inventor： Hideki Osaka ,  Toyohiko Komatsu

    IPC: G06F1750

    CPC classification number: H01P5/185 ,  G06F17/5036 ,  G06F17/5068 ,  H01P5/187 ,  H05K1/0239 ,  H05K3/0005

    Abstract: The number of steps for preparing a layout diagram of a circuit including a coupler, which is formed by arranging a main line and a stub line in parallel with each other, is reduced. A circuit diagram editor 1902 arranges a coupler symbol 100 stored in a component symbol storage section 1904 when the coupler is arranged in preparing a circuit diagram. A layout section 1935 of a layout diagram editor 1922 layouts two wirings constituting the coupler by use of circuit diagram information and coupler information in which a coupler length and a coupler interval are defined. An object extraction section 1937 of a wiring check section 1936 extracts components and wirings from the layout diagram, and passes these to a wiring checker 1938. At this time, the coupler is passed to the wiring checker as one component that cannot be decomposed no more. Therefore, an interval between two wirings constituting the coupler is not checked.

    Abstract translation: 减少了通过将主线和短线布置成彼此平行而形成的包括耦合器的电路布局图的步骤数。 当制造电路图时，电路图编辑器1902布置存储在元件符号存储部分1904中的耦合器符号100。 布局图编辑器1922的布局部分1935通过使用其中限定了耦合器长度和耦合器间隔的电路图信息和耦合器信息来布置构成耦合器的两个布线。 布线检查部1936的物体提取部1937从布局图中提取部件和布线，并将其传递到布线检查器1938.此时，耦合器作为不能分解的一个部件被传递到布线检查器 。 因此，不检查构成耦合器的两条布线之间的间隔。

    Accessible network of performance index tables
    29.
    发明授权
    Accessible network of performance index tables 失效
    性能指标表可访问网络

    公开(公告)号：US06519640B2

    公开(公告)日：2003-02-11

    申请号：US10082185

    申请日：2002-02-26

    Applicant: Ryuichi Hattori ,  Toshihiko Ogura ,  Takashi Oeda ,  Koichi Okazawa ,  Hideki Osaka ,  Tsunehiro Tobita ,  Tsutomu Hara

    Inventor： Ryuichi Hattori ,  Toshihiko Ogura ,  Takashi Oeda ,  Koichi Okazawa ,  Hideki Osaka ,  Tsunehiro Tobita ,  Tsutomu Hara

    IPC: G06F1516

    CPC classification number: G06F9/5055 ,  G06F9/5044 ,  G06F2209/5015 ,  H04L29/12047 ,  H04L41/5009 ,  H04L61/15 ,  H04L67/36

    Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

    Abstract translation: 在通过网络彼此连接的每个信息处理设备中，布置了其功能和性能被注册到其中的服务质量（QOS）表。 当信息处理设备另外与网络链接时，其QOS表被自动地注册到网络的本地目录，使得代理将QOS表的内容转换成要经由用户界面提供给用户的服务信息 。 由于操作，连接到网络的每个信息处理设备的功能和性能的信息被转换成用户的服务信息。 因此，用户可以更多地直接接收必要的服务。

    Information processor and method of its component arrangement
    30.
    发明授权
    Information processor and method of its component arrangement 失效
    信息处理器及其组件安装方法

    公开(公告)号：US6108731A

    公开(公告)日：2000-08-22

    申请号：US117741

    申请日：1998-08-04

    Applicant: Shinichi Suzuki ,  Tsunehiro Tobita ,  Yoshitsugu Ichieda ,  Hiroyuki Hodo ,  Mihoko Kudou ,  Tetsuo Hiramitsu ,  Hideki Osaka ,  Tsutomu Hara

    Inventor： Shinichi Suzuki ,  Tsunehiro Tobita ,  Yoshitsugu Ichieda ,  Hiroyuki Hodo ,  Mihoko Kudou ,  Tetsuo Hiramitsu ,  Hideki Osaka ,  Tsutomu Hara

    IPC: G06F1/18 ,  G06F13/00

    CPC classification number: G06F1/185 ,  G06F1/184 ,  G06F1/186

    Abstract: A plurality of processor elements (31 to 34) are disposed on a main board (710) in line in parallel with a first edge of the main substrate (710). Expansion board slots (331 to 336) into which an expansion board for mounting an I/O interface thereon is plugged and a memory connector (341) to which a memory board for mounting a memory thereon is connected are disposed in a region of the main substrate opposite to the first edge. The long sides of the expansion board slots (331 to 336) and the memory board connector (341) are in parallel with the first edge. A bridge LSI for executing protocol conversion between processor buses (210, 211, 212) and an I/O bus (230) and memory controllers (151, 152) for controlling memory access are disposed in regions adjacent to both the expansion board slots and the processor elements. The processor bus (210, 211, 212) is bent into a protuberance shape so that a branch does not substantially form and the bridge LSI and memory controller are substantially at the middle portion of a plurality of processors. The processor bus connects the processor elements, the bridge LSI and the memory controller in this order.

    Abstract translation: PCT No.PCT / JP96 / 00285 Sec。 371日期：1998年8月4日 102（e）1998年8月4日PCT PCT 1996年2月9日PCT公布。 出版物WO97 / 29415 日期1997年8月14日多个处理器元件（31〜34）与主基板（710）的第一边缘平行配置在主板（710）上。 在其上插入有用于安装I / O接口的扩展板的扩展板插槽（331至336）和连接有用于安装其上的存储器的存储器板的存储器连接器（341）设置在主体的区域中 基板与第一边缘相对。 扩展板槽（331〜336）和存储板连接器（341）的长边与第一边缘平行。 用于在处理器总线（210,211,212）和用于控制存储器存取的I / O总线（230）和存储器控制器（151,152）之间执行协议转换的桥式LSI被布置在与扩展板插槽和 处理器元件。 处理器总线（210,211,212）弯曲成突起形状，使得分支基本上不形成，并且桥接器LSI和存储器控制器基本上位于多个处理器的中间部分。 处理器总线按顺序连接处理器元件，桥接器LSI和存储器控制器。

Patent Agency Ranking