公开(公告)号：US10692759B2

公开(公告)日：2020-06-23

申请号：US16037985

申请日：2018-07-17

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  He Ren ,  Hao Chen ,  Mehul B. Naik

IPC: H01L21/768 ,  H01L21/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  C23F1/00 ,  H01L49/02

Abstract: Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.

公开(公告)号：US20180144973A1

公开(公告)日：2018-05-24

申请号：US15800784

申请日：2017-11-01

Applicant: Applied Materials, Inc.

Inventor： Weifeng Ye ,  Jiang Lu ,  Feng Chen ,  Zhiyuan Wu ,  Kai Wu ,  Vikash Banthia ,  He Ren ,  Sang Ho Yu ,  Mei Chang ,  Feiyue Ma ,  Yu Lei ,  Keyvan Kashefizadeh ,  Kevin Moraes ,  Paul F. Ma ,  Hua Ai

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7685 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53238

Abstract: Methods to selectively deposit capping layers on a copper surface relative to a dielectric surface comprising separately the copper surface to a cobalt precursor gas and a tungsten precursor gas, each in a separate processing chamber. The copper surface and the dielectric surfaces can be substantially coplanar. The combined thickness of cobalt and tungsten capping films is in the range of about 2 Å to about 60 Å.

公开(公告)号：US20170372960A1

公开(公告)日：2017-12-28

申请号：US15700631

申请日：2017-09-11

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Huixiong Dai ,  Yongmei Chen ,  He Ren ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532

Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.

公开(公告)号：US09601431B2

公开(公告)日：2017-03-21

申请号：US14173807

申请日：2014-02-05

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Mehul B. Naik ,  Yong Cao ,  Mei-yee Shek ,  Yana Cheng ,  Sree Rangasai V. Kesapragada

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L23/53238 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer.

公开(公告)号：US09384997B2

公开(公告)日：2016-07-05

申请号：US14602835

申请日：2015-01-22

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Jang-Gyoo Yang ,  Jonghoon Baek ,  Anchuan Wang ,  Soonam Park ,  Saurabh Garg ,  Xinglong Chen ,  Nitin K. Ingle

IPC: H01L21/302 ,  H01L21/311 ,  H01J37/32

CPC classification number: H01L21/31116 ,  H01J37/32357

Abstract: A method of etching exposed patterned heterogeneous structures is described and includes a remote plasma etch formed from a reactive precursor. The plasma power is pulsed rather than left on continuously. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents selectively remove one material faster than another. The etch selectivity results from the pulsing of the plasma power to the remote plasma region, which has been found to suppress the number of ionically-charged species that reach the substrate. The etch selectivity may also result from the presence of an ion suppression element positioned between a portion of the remote plasma and the substrate processing region.

公开(公告)号：US09269563B2

公开(公告)日：2016-02-23

申请号：US14298102

申请日：2014-06-06

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Mehul B. Naik

IPC: H01L21/02 ,  H01L23/00 ,  H01L21/033

CPC classification number: H01L21/02063 ,  H01J37/321 ,  H01J37/32477 ,  H01J37/32642 ,  H01J37/32715 ,  H01L21/0337 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/76808 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatuses for forming a dual damascene structure utilizing a selective protection process to protect vias and/or trenches in the dual damascene structure while removing a hardmask layer from the dual damascene structure. In one embodiment, a method for removing a patterned hardmask layer from a substrate includes forming an organic polymer material on a dual damascene structure that exposes substantially a patterned hardmask layer disposed on an upper surface of the dual damascene structure, removing the patterned hardmask layer on the substrate, and removing the organic polymer material from the substrate.

Abstract translation: 用于形成双镶嵌结构的方法和装置，其利用选择性保护过程来保护双镶嵌结构中的通孔和/或沟槽，同时从双镶嵌结构去除硬掩模层。 在一个实施例中，用于从衬底去除图案化硬掩模层的方法包括在双镶嵌结构上形成有机聚合物材料，其暴露基本上设置在双镶嵌结构的上表面上的图案化硬掩模层， 并且从衬底去除有机聚合物材料。

公开(公告)号：US08969212B2

公开(公告)日：2015-03-03

申请号：US13834206

申请日：2013-03-15

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Jang-Gyoo Yang ,  Jonghoon Baek ,  Anchuan Wang ,  Soonam Park ,  Saurabh Garg ,  Xinglong Chen ,  Nitin K. Ingle

IPC: H01L21/302 ,  H01L21/311 ,  H01J37/32

CPC classification number: H01L21/31116 ,  H01J37/32357

Abstract: A method of etching exposed patterned heterogeneous structures is described and includes a remote plasma etch formed from a reactive precursor. The plasma power is pulsed rather than left on continuously. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents selectively remove one material faster than another. The etch selectivity results from the pulsing of the plasma power to the remote plasma region, which has been found to suppress the number of ionically-charged species that reach the substrate. The etch selectivity may also result from the presence of an ion suppression element positioned between a portion of the remote plasma and the substrate processing region.

Abstract translation: 描述了蚀刻暴露的图案化异质结构的方法，并且包括由反应性前体形成的远程等离子体蚀刻。 等离子体功率是脉冲的，而不是连续地保持。 来自远程等离子体的等离子体流出物流入衬底处理区域，其中等离子体流出物选择性地比另一种更快地去除一种材料。 蚀刻选择性是由等离子体功率脉冲到远程等离子体区域而产生的，这已经被发现抑制了到达衬底的离子充电物质的数量。 蚀刻选择性也可能由位于远程等离子体的一部分与基板处理区域之间的离子抑制元件的存在引起。

公开(公告)号：US20230045689A1

公开(公告)日：2023-02-09

申请号：US17968201

申请日：2022-10-18

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  Chi Lu ,  He Ren ,  Chi-I Lang ,  Ho-yung David Hwang ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/027

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

公开(公告)号：US11515200B2

公开(公告)日：2022-11-29

申请号：US17110826

申请日：2020-12-03

Applicant: Applied Materials, Inc.

Inventor： Yi Xu ,  Yufei Hu ,  He Ren ,  Yu Lei ,  Shi You ,  Kazuya Daito

IPC: H01L21/768

Abstract: Embodiments of the disclosure provide methods which reduce or eliminate lateral growth of a selective tungsten layer. Further embodiments provide an integrated clean and deposition method which improves the selectivity of selectively deposited tungsten on trench structures. Additional embodiments provide methods for forming a more uniform and selective bottom-up gap fill for trench structures with improved film properties.

公开(公告)号：US20210351032A1

公开(公告)日：2021-11-11

申请号：US16867554

申请日：2020-05-05

Applicant: Applied Materials, Inc.

Inventor： Xi Cen ,  Yakuan Yao ,  Yiming Lai ,  Kai Wu ,  Avgerinos V. Gelatos ,  David T. Or ,  Keyvan Kashefi ,  Yu Lei ,  Lin Dong ,  He Ren ,  Yi Xu ,  Mehul Naik ,  Hao Chen ,  Mang-Mang Ling

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/67

Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.