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公开(公告)号:US20210203094A1
公开(公告)日:2021-07-01
申请号:US17202961
申请日:2021-03-16
Applicant: Intel Corporation
Inventor: Xiang Li , Mo Liu , Shaohua Li , Jingbo Li , Kai Xiao
Abstract: In one embodiment, a card edge connector includes: a housing having an opening into which a first circuit board is to be inserted; a plurality of pins each having a first end and a second end, the plurality of pins extending from within the opening through a bottom surface of the housing, the first end of the first plurality of pins to mate with a corresponding contact of the first circuit board; and a plurality of ball grid array (BGA) solder balls each adapted at the second end of a corresponding one of the plurality of pins, the plurality of pins to mate with a corresponding conductive area of a second circuit board to which the card edge connector mates via the plurality of BGA solder balls. Other embodiments are described and claimed.
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公开(公告)号:US10467160B2
公开(公告)日:2019-11-05
申请号:US15719742
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Xiang Li , Yunhui Chu , Jun Liao , George Vergis , James A. McCall , Charles C. Phares , Konika Ganguly , Qin Li
Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.
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公开(公告)号:US10342132B2
公开(公告)日:2019-07-02
申请号:US15839419
申请日:2017-12-12
Applicant: INTEL CORPORATION
Inventor: Xiang Li , George Vergis , Slobodan Mrdjan
IPC: H05K7/00 , H05K5/00 , H05K1/14 , H05K1/02 , H05K3/46 , H01R12/70 , H01R12/55 , H01R12/52 , H01R12/73
Abstract: Embodiments of the present disclosure are directed towards a memory device insertable into a PCB, e.g., a motherboard of a computing device. In some embodiments, the memory device may include a first PCB having a first thickness, to house one or more memory modules disposed on at least one side of the first PCB. The memory device may further include a layer having a second thickness, which may be attached to the side of the first PCB in an area that is proximate to an edge of the first PCB, to form a memory device portion that may be insertable into a connector slot disposed on a second PCB. The insertable portion may have a thickness that comprises the first and second thicknesses, to fit into the connector slot of the second PCB. Other embodiments may be described and/or claimed.
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公开(公告)号:US10305207B2
公开(公告)日:2019-05-28
申请号:US15622001
申请日:2017-06-13
Applicant: INTEL CORPORATION
Inventor: Xiang Li , George Vergis
Abstract: A surface mount connector includes a housing including inner surfaces surrounding a card edge region, and outer surfaces defining an exterior region. The connector also includes a recess in at least one of the outer surfaces, the recess sized to accept a removably engageable arm therein. The connector also defines a cross-sectional width that is smaller in the recess than at a position adjacent to the recess. Other embodiments are described and claimed.
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公开(公告)号:US09935384B1
公开(公告)日:2018-04-03
申请号:US15280281
申请日:2016-09-29
Applicant: Intel Corporation
Inventor: Xiang Li , George Vergis , John M. Lynch
IPC: H01R13/62 , H01R12/70 , H01R13/633 , H01R12/73 , H01R43/20
CPC classification number: H01R12/7058 , H01R12/721 , H01R12/737 , H01R13/6335 , H01R43/205 , H05K7/1409
Abstract: A circuit board may include a connector having a circuit module latch that may include a latch frame and pivot-able ejector assembly coupled to the latch frame.
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公开(公告)号:US20170271818A1
公开(公告)日:2017-09-21
申请号:US15074094
申请日:2016-03-18
Applicant: Intel Corporation
Inventor: John M. Lynch , Chong Richard Zhao , Xiang Li , Donald T. Tran
IPC: H01R13/6461 , H01R12/75 , H01R12/73
CPC classification number: H01R13/6461 , H01R12/72 , H01R12/721 , H01R12/73 , H01R12/737 , H01R12/75 , H01R13/658 , H01R13/6585 , H01R13/6586 , H01R23/6873
Abstract: An example electronic assembly for securing an electronic card. In some forms, the electronic assembly further includes a printed circuit board. The electronic assembly includes a housing having a first set of electrical contacts and a second set of electrical contacts. The housing is configured to receive the electronic card between the first and second set of electrical contacts. The housing further includes a third set of electrical contacts and a fourth set of electrical contacts. The housing is configured to receive the electronic card between the third and fourth set of electrical contacts. A ground shield is positioned between at least one of the first and third set of electrical contacts and the second and fourth set of electrical contacts. In some forms, the ground shield may be positioned between both the first and third set of electrical contacts and the second and fourth set of electrical contacts.
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公开(公告)号:US09661657B2
公开(公告)日:2017-05-23
申请号:US14314397
申请日:2014-06-25
Applicant: Intel Corporation
Inventor: Yifan Yu , Xiang Li , Guangjie Li , Xu Zhang
IPC: H04J3/16 , H04W74/04 , H04L5/00 , H04L5/14 , H04W72/04 , H04W52/02 , H04W76/04 , H04L1/18 , H04L29/08 , H04W40/30 , H04L12/825 , H04W28/02 , H04W16/14 , H04B7/26 , H04L27/26 , H04W72/02 , H04L1/00 , H04W88/06 , H04W88/10 , H04W36/00 , H04W84/12
CPC classification number: H04W74/04 , H04B7/2621 , H04L1/0026 , H04L1/1825 , H04L5/0007 , H04L5/0032 , H04L5/0051 , H04L5/0073 , H04L5/14 , H04L27/2607 , H04L47/25 , H04L69/161 , H04L69/163 , H04L69/321 , H04L69/324 , H04L69/326 , H04W16/14 , H04W28/0205 , H04W36/0083 , H04W40/30 , H04W52/0216 , H04W52/0254 , H04W72/02 , H04W72/0413 , H04W72/042 , H04W72/0446 , H04W72/0453 , H04W72/048 , H04W76/27 , H04W76/28 , H04W80/06 , H04W84/12 , H04W88/06 , H04W88/10 , Y02D50/00 , Y02D70/00 , Y02D70/1222 , Y02D70/1224 , Y02D70/1226 , Y02D70/1242 , Y02D70/1244 , Y02D70/1246 , Y02D70/1262 , Y02D70/1264 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/164 , Y02D70/166 , Y02D70/168 , Y02D70/21 , Y02D70/22 , Y02D70/23 , Y02D70/24
Abstract: Embodiments described herein relate generally to efficient transmission of data over a radio network between a user equipment (“UE”) and a network node. The UE may adapt packets from TCP to a private protocol and transmit those data packets to the network node. The UE may use ARQ data from link layer circuitry to locally generate TCP ACK data for TCP layer circuitry. At the network node, the private-protocol data packets may be adapted to TCP and transmitted to a remote host over the Internet so that the TCP semantic may be maintained between the UE and the remote host. Other embodiments may be described and/or claimed.
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公开(公告)号:US12300931B2
公开(公告)日:2025-05-13
申请号:US17352211
申请日:2021-06-18
Applicant: Intel Corporation
Inventor: Xiang Li , George Vergis
IPC: H01R13/633 , H01R12/73 , H01R13/635
Abstract: An apparatus is described. The apparatus includes a dual-in line memory module (DIMM) socket having a first latch and a second latch. One of the first latch and the second latch having a feature for a user to apply force to release a DIMM from the DIMM socket. The other of the first latch and the second latch not having a feature for the user to apply force so that one end of the DIMM releases before an opposite end of the DIMM during release of the DIMM from the DIMM socket.
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公开(公告)号:US20240260233A1
公开(公告)日:2024-08-01
申请号:US18565880
申请日:2021-11-11
Applicant: Intel Corporation
Inventor: Ming Zhang , Yuehong Fan , Peng Wei , Chuanlou Wang , Rajiv K. Mongia , Guocheng Zhang , Yingqiong Bu , Berhanu Wondimu , Guixiang Tan , Xiang Que , Qing Jiang , Liu Yu , Wei-Ming Chu , Chen Zhang , Hao Zhou , Feng Qi , Catharina Biber , Devdatta Prakash Kulkarni , Xiang Li , Yechi Zhang
IPC: H05K7/20 , G06F1/20 , H01L23/40 , H01L23/427 , H01L23/473
CPC classification number: H05K7/20336 , G06F1/20 , H01L23/4093 , H01L23/427 , H01L23/473 , G06F2200/201
Abstract: Heat pipes and vapor chambers that are components of a DIMM cooling assembly are described.
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公开(公告)号:US11984685B2
公开(公告)日:2024-05-14
申请号:US17001113
申请日:2020-08-24
Applicant: Intel Corporation
Inventor: Phil Geng , Xiang Li , George Vergis , Mani Prakash
IPC: H01R13/629 , H01R12/72 , H01R13/631 , H01R13/635 , H05K5/02
CPC classification number: H01R13/62988 , H01R12/721 , H01R13/631 , H01R13/635 , H05K5/0295
Abstract: An embodiment of a latch apparatus for a circuit board comprises a first latch body with a retention mechanism for the circuit board, a second latch body with a coupling mechanism for a connector, and a spring mechanism mechanically coupled between the first latch body and the second latch body. Other embodiments are disclosed and claimed.
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