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    TRANSCEIVER ARRAY
    21.
    发明申请
    TRANSCEIVER ARRAY 审中-公开

    公开(公告)号：US20190020400A1

    公开(公告)日：2019-01-17

    申请号：US16130644

    申请日：2018-09-13

    Applicant: Maxlinear, Inc.

    Inventor： Curtis Ling ,  Sheng Ye

    IPC: H04B7/08 ,  H04B17/00 ,  H04B10/40 ,  H01Q3/24

    Abstract: Each of a plurality of modules comprises a respective one of a plurality of antenna elements, and each of a subset of the plurality of modules comprising a respective one of a plurality of transceivers, wherein the plurality of modules are interconnected via one or more communication links. The circuitry may be operable to receive a calibration signal via the plurality of antenna elements, determine, for each one of the antenna elements, a time and/or phase of arrival of the calibration signal, calculate, based on the time and/or phase of arrival of the calibration signal at each of the plurality of antenna elements, electrical distances between the plurality of antenna elements on the one or more communication links, and calculate beamforming coefficients for use with the plurality of antenna elements based on the electrical distances.

    Method and system for a sampled loop filter in a phase locked loop (PLL)
    23.
    发明授权
    Method and system for a sampled loop filter in a phase locked loop (PLL) 有权

    公开(公告)号：US09906227B2

    公开(公告)日：2018-02-27

    申请号：US15236369

    申请日：2016-08-12

    Applicant: Maxlinear, Inc.

    Inventor： Sangeetha Gopalakrishnan ,  Sheng Ye ,  Vamsi Paidi

    IPC: H03L7/00 ,  H03L7/085 ,  H03L7/197 ,  H03L7/093 ,  H03L7/099

    CPC classification number: H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/1974 ,  H03L7/1976

    Abstract: Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

    Reference-frequency-insensitive phase locked loop
    25.
    发明授权
    Reference-frequency-insensitive phase locked loop 有权
    参考频率不敏感的锁相环

    公开(公告)号：US09537494B2

    公开(公告)日：2017-01-03

    申请号：US14860262

    申请日：2015-09-21

    Applicant: MaxLinear, Inc.

    Inventor： Sheng Ye

    IPC: H03L7/08 ,  H03L7/093 ,  H03L7/085 ,  H03L7/18

    CPC classification number: H03L7/093 ,  H03L7/08 ,  H03L7/085 ,  H03L7/0891 ,  H03L7/18 ,  H03L2207/10

    Abstract: A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. A sampled loop filter (SLPF) in the phase locked loop may capture charge from a charge pump (CHP) in the phase locked loop and the charge is captured at a frequency corresponding to the frequency of the reference clock signal. A switch of the sampled loop filter is utilized and controlled to manage holding and releasing of the captured charge, where the switch is controlled utilizing a control signal. By utilizing the sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of the charge pump, disturbance which is associated with duty cycle errors of the crystal clock signal.

    Abstract translation: 锁相环可以用于利用倍频器产生频率为晶体时钟信号频率的两倍的参考时钟信号，并被键入晶体时钟信号的上升沿和下降沿。 锁相环中的采样环路滤波器（SLPF）可以在锁相环中从电荷泵（CHP）捕获电荷，并以与参考时钟信号的频率对应的频率捕获电荷。 利用和控制采样环路滤波器的开关来管理捕获的电荷的保持和释放，其中使用控制信号来控制开关。 通过在锁相环中利用采样环路滤波器，锁相环可以在电荷泵的输出处消除与晶体时钟信号的占空比误差相关的干扰。

    OUTDOOR UNIT RESONATOR CORRECTION
    27.
    发明申请
    OUTDOOR UNIT RESONATOR CORRECTION 有权

    公开(公告)号：US20160127119A1

    公开(公告)日：2016-05-05

    申请号：US14976529

    申请日：2015-12-21

    Applicant: Maxlinear, Inc.

    Inventor： Subramanian Anantharaman Chandrasekarapuram ,  Anand Anandakumar ,  Stephane Laurent-Michel ,  Sheng Ye ,  Raja Pullela ,  Glenn Chang ,  Vamsi Paidi

    IPC: H04L7/00

    CPC classification number: H04B1/1027

    Abstract: A system comprises a microwave backhaul outdoor unit having a first resonant circuit, phase error determination circuitry, and phase error compensation circuitry. The first resonant circuit is operable to generate a first signal characterized by a first amount of phase noise and a first amount of temperature stability. The phase error determination circuitry is operable to generate a phase error signal indicative of phase error between the first signal and a second signal, wherein the second signal is characterized by a second amount of phase noise that is greater than the first amount of phase noise, and the second signal is characterized by a second amount of temperature instability that is less than the first amount of temperature instability. The phase error compensation circuitry is operable to adjust the phase of a data signal based on the phase error signal, the adjustment resulting in a phase compensated signal.

    Method and system for Time Interleaved Analog-To-Digital Converter Timing Mismatch Estimation And Compensation
    28.
    发明申请
    Method and system for Time Interleaved Analog-To-Digital Converter Timing Mismatch Estimation And Compensation 有权
    时间交错模数转换器时序不匹配估计和补偿的方法和系统

    公开(公告)号：US20160043731A1

    公开(公告)日：2016-02-11

    申请号：US14920699

    申请日：2015-10-22

    Applicant: Maxlinear, Inc.

    Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumer ,  Sheng Ye ,  Timothy Leo Gallagher

    IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12

    CPC classification number: H03M1/0612 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/1215 ,  H03M1/50 ,  H04L7/0087 ,  H04L25/08 ,  H04W56/00

    Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

    Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 以及通过估计期望的数字输出信号和阻塞信号之间的复数耦合系数，将在时间交错ADC中的定时偏移上的混叠在期望信号上的阻塞信号减少。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。

    Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation
    29.
    发明授权
    Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation 有权
    时间交错模数转换器定时失配估计和补偿的方法和系统

    公开(公告)号：US09172386B2

    公开(公告)日：2015-10-27

    申请号：US14590250

    申请日：2015-01-06

    Applicant: Maxlinear, Inc.

    Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumar ,  Sheng Ye ,  Timothy Leo Gallagher

    IPC: H03M1/06 ,  H03M1/50 ,  H03M1/10 ,  H03M1/12 ,  H04L7/00 ,  H04L25/08

    CPC classification number: H03M1/0612 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/1215 ,  H03M1/50 ,  H04L7/0087 ,  H04L25/08 ,  H04W56/00

    Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

    Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 并且通过估计期望的数字输出信号和阻塞信号之间的复耦合系数来减少由时间交错ADC中的定时偏移产生的阻塞信号。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。

    Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs)
    30.
    发明授权
    Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) 有权
    用于异步逐次逼近寄存器（SAR）模数转换器（ADC）的方法和系统

    公开(公告)号：US09136859B2

    公开(公告)日：2015-09-15

    申请号：US14585656

    申请日：2014-12-30

    Applicant: MaxLinear, Inc.

    Inventor： Eric Fogleman ,  Sheng Ye ,  Xuefeng Chen ,  Kok Lim Chan

    IPC: H03M1/34 ,  H03M1/12 ,  H03M1/46 ,  H03M1/06

    CPC classification number: H03M1/0617 ,  H03M1/001 ,  H03M1/069 ,  H03M1/125 ,  H03M1/46 ,  H03M1/462

    Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

    Abstract translation: 在每个数模转换器（DAC）码字中利用一个或多个重叠冗余位的异步逐次逼近寄存器模数转换器（SAR ADC）可操作以产生指示每个数 - 模转换器 比较步骤，表示每个比较步骤的输出决定是有效的。 可以基于产生的指示信号来启动定时器。 可以产生超时信号，该超时信号抢占指示信号并强制先占决定，其中先占决定将一个或多个剩余的比特设置为相应的数模转换器中的一个或多个重叠的冗余比特，但不包括其中的一个或多个重叠的冗余比特 用于当前比较步骤的代码字到特定值。 例如，可以将一个或多个剩余比特设置为从在紧接的前一决定中确定的比特的值导出的值。

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