公开(公告)号：US20200212019A1

公开(公告)日：2020-07-02

申请号：US16817001

申请日：2020-03-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Rui Wu ,  Fu-Tang Huang ,  Chia-Cheng Chen ,  Chun-Hsien Lin ,  Hsuan-Hao Mi ,  Yu-Cheng Pai

IPC: H01L25/10 ,  H01L23/24 ,  H01L23/498 ,  H01L25/00

Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.

公开(公告)号：US10431535B2

公开(公告)日：2019-10-01

申请号：US15680515

申请日：2017-08-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jui-Feng Chen ,  Chia-Cheng Hsu ,  Wen-Jung Tsai ,  Chia-Cheng Chen ,  Cheng Kai Chang

IPC: H01L21/44 ,  H01L29/40 ,  H01L23/498 ,  H01L23/48 ,  H01Q1/22

Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming an antenna structure in contact with one side of a circuit structure of a packaging substrate, and disposing an electronic component on the other side of the circuit structure. As such, the antenna structure is integrated with the packaging substrate, thereby reducing the thickness of the electronic package and improving the efficiency of the antenna structure.

公开(公告)号：US20190164941A1

公开(公告)日：2019-05-30

申请号：US15938271

申请日：2018-03-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Rui Wu ,  Fu-Tang Huang ,  Chia-Cheng Chen ,  Chun-Hsien Lin ,  Hsuan-Hao Mi ,  Yu-Cheng Pai

IPC: H01L25/10 ,  H01L23/498 ,  H01L25/00 ,  H01L23/24

Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.

公开(公告)号：US10043757B2

公开(公告)日：2018-08-07

申请号：US14708249

申请日：2015-05-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Shih-Chao Chiu ,  Chun-Hsien Lin ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L29/40 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.

公开(公告)号：US20160099204A1

公开(公告)日：2016-04-07

申请号：US14709510

申请日：2015-05-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Chia-Cheng Chen ,  Chih-Jen Yang ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H05K1/11 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17106 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/18161 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K1/111 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package structure is provided, including: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having a height greater than a height of each of the conductive traces; and an electronic component disposed on and electrically connected to the conductive pads via a plurality of conductive elements, wherein at least one of the conductive traces is positioned in proximity of at least one of the conductive pads. Therefore, the conductive elements are prevented from being in contact with the conductive traces, and the problem that the conductive pads and the conductive traces are shorted is solved. The present invention further provides a method for fabricating the packaging substrate.

Abstract translation: 提供一种封装结构，包括：具有多个导电迹线的板; 多个导电焊盘，其形成在所述板上并且每个具有高于每个所述导电迹线的高度的高度; 以及电子部件，其经由多个导电元件设置在导电焊盘上并与其电连接，其中至少一个导电迹线位于至少一个导电焊盘附近。 因此，防止了导电元件与导电迹线接触，解决了导电焊盘和导电迹线短路的问题。 本发明还提供一种制造封装基板的方法。

公开(公告)号：US20160079151A1

公开(公告)日：2016-03-17

申请号：US14692769

申请日：2015-04-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H05K1/18 ,  H05K3/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H05K3/32

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

Abstract translation: 本发明提供一种具有嵌入式电子部件的封装结构和制造封装结构的方法。 该方法包括：在载体上形成第一布线层; 移除载体并在键合载体上形成第一布线层; 在第一布线层上设置电子部件; 在所述第一布线层上形成封装层，第二布线层和绝缘层; 在所述电子部件和所述第二布线层上设置芯片; 并形成覆盖芯片的覆盖层。 本发明可以有效地减少包装结构和电子部件的厚度而不使用粘合剂。

公开(公告)号：US20150333029A1

公开(公告)日：2015-11-19

申请号：US14459713

申请日：2014-08-14

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-cheng Pai ,  Chun- Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2924/0002

Abstract: A package substrate and a method of fabricating the same are provided. The method includes providing a substrate body having a first surface, a second surface opposing the first surface, a plurality of first electrical connecting pads disposed on the first surface; mounting a metal board on the first electrical connecting pads; and patterning the metal board so as to define a plurality of metal pillars corresponding to the first electrical connecting pads. Therefore, drawbacks of raw edges and unequal heights of the metal pillars can be obviated.

Abstract translation: 提供封装基板及其制造方法。 该方法包括提供具有第一表面，与第一表面相对的第二表面的衬底主体，设置在第一表面上的多个第一电连接焊盘; 将金属板安装在第一电连接垫上; 以及图案化所述金属板以限定对应于所述第一电连接焊盘的多个金属柱。 因此，可以消除金属柱的原始边缘和不等高度的缺点。

公开(公告)号：US09082723B2

公开(公告)日：2015-07-14

申请号：US14143700

申请日：2013-12-30

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Tzu-Chieh Chen ,  Shih-Chao Chiu ,  Chia-Cheng Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L24/32 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/16245 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a first dielectric layer having opposite first and second surfaces and a cavity penetrating the first and second surfaces; a first circuit layer embedded in the first dielectric layer and exposed from the first surface of the first dielectric layer; at least an adhesive member formed in the cavity and adjacent to the first surface of the first dielectric layer; an electronic element disposed on the adhesive member; a second dielectric layer formed on the second surface of the first dielectric layer and in the cavity to encapsulate the adhesive member and the electronic element; a second circuit layer formed on the second dielectric layer; and a plurality of conductive vias formed in the second dielectric layer for electrically connecting the second circuit layer and the electronic element, thereby reducing the package size and cost and increasing the wiring space and flexibility.

Abstract translation: 提供一种半导体封装，其包括：具有相对的第一和第二表面的第一介电层和穿透第一表面和第二表面的空腔; 第一电路层，其被嵌入在所述第一电介质层中并从所述第一介电层的所述第一表面露出; 至少形成在所述空腔中并且与所述第一介电层的所述第一表面相邻的粘合构件; 设置在所述粘合构件上的电子元件; 第二电介质层，形成在所述第一介电层的所述第二表面上并且在所述空腔中，以封装所述粘合剂构件和所述电子元件; 形成在所述第二电介质层上的第二电路层; 以及形成在第二电介质层中的多个导电通孔，用于电连接第二电路层和电子元件，由此减小封装尺寸和成本并增加布线空间和柔性。

公开(公告)号：US20150102484A1

公开(公告)日：2015-04-16

申请号：US14136238

申请日：2013-12-20

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD

Inventor： Chia-Cheng Chen ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Liang-yi Hung ,  Wei-chung Hsiao ,  Yu-cheng Pai ,  Shih-Chao Chiu ,  Don-Son Jiang ,  Yi-Feng Chang ,  Lung-Yuan Wang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/535

CPC classification number: H01L25/105 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/1011 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H05K1/181 ,  H05K1/183 ,  H05K3/284 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A package structure is disclosed, which includes: a first substrate; a build-up layer formed on and electrically connected to the first substrate and having a cavity; at least an electronic element disposed in the cavity and electrically connected to the first substrate; a stack member disposed on the build-up layer so as to be stacked on the first substrate; and an encapsulant formed between the build-up layer and the stack member. The build-up layer facilitates to achieve a stand-off effect and prevent solder bridging.

Abstract translation: 公开了一种封装结构，其包括：第一基板; 形成在第一基板上并电连接到第一基板并具有空腔的积聚层; 至少电子元件设置在所述空腔中并电连接到所述第一基板; 堆叠构件，其设置在堆积层上以堆叠在第一基板上; 以及形成在堆积层和堆叠构件之间的密封剂。 堆积层有助于实现隔离效应并防止焊料桥接。

公开(公告)号：US20180316083A1

公开(公告)日：2018-11-01

申请号：US15680515

申请日：2017-08-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jui-Feng Chen ,  Chia-Cheng Hsu ,  Wen-Jung Tsai ,  Chia-Cheng Chen ,  Cheng Kai Chang

IPC: H01Q1/22 ,  H01L23/498 ,  H01L23/66 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/481 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01Q1/2283 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming an antenna structure in contact with one side of a circuit structure of a packaging substrate, and disposing an electronic component on the other side of the circuit structure. As such, the antenna structure is integrated with the packaging substrate, thereby reducing the thickness of the electronic package and improving the efficiency of the antenna structure.