公开(公告)号：US20080311360A1

公开(公告)日：2008-12-18

申请号：US11640498

申请日：2006-12-18

Applicant: Yukihisa Kitagawa

Inventor： Yukihisa Kitagawa

IPC: B32B3/10 ,  B32B37/00

CPC classification number: H01L24/85 ,  H01L23/498 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48699 ,  H01L2224/48739 ,  H01L2224/48764 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/092 ,  H05K3/248 ,  H05K2201/035 ,  H05K2203/049 ,  Y10T156/10 ,  Y10T428/24917 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A thick film circuit component has a thick film electrode interconnect which allows an electrode on a semiconductor chip and an aluminum wire to be directly bonded to each other with a sufficient bonding strength. The thick film circuit component has an insulated substrate 11 and a thick film electrode interconnect 12 disposed on the substrate. The thick film electrode interconnect 12 includes a bonding area for an aluminum wire, the bonding area comprising an Ag-Pt thick film 12a disposed as a lower layer and an Ag-Pd thick film 12b disposed as an upper layer. The bonding area comprises the Ag-Pt thick film 12a and the Ag-Pd thick film 12b, which are fused together.

Abstract translation: 厚膜电路部件具有厚膜电极互连，其允许半导体芯片和铝线上的电极以足够的接合强度彼此直接接合。 厚膜电路部件具有设置在基板上的绝缘基板11和厚膜电极互连12。 厚膜电极互连12包括铝线的接合区域，该接合区域包括设置为下层的Ag-Pt厚膜12a和设置为上层的Ag-Pd厚膜12b。 接合区域包括熔合在一起的Ag-Pt厚膜12a和Ag-Pd厚膜12b。

公开(公告)号：US20080298036A1

公开(公告)日：2008-12-04

申请号：US12130255

申请日：2008-05-30

Applicant: Hiroshi YAMAZAKI ,  Taiki SUEYOSHI

Inventor： Hiroshi YAMAZAKI ,  Taiki SUEYOSHI

IPC: H01R12/16 ,  H01M2/08

CPC classification number: H05K3/249 ,  H01M8/0206 ,  H01M8/0221 ,  H01M8/0228 ,  H01M8/04201 ,  H01M8/1011 ,  H01M8/1097 ,  H05K1/0272 ,  H05K1/16 ,  H05K3/06 ,  H05K2201/035 ,  H05K2201/056 ,  Y02E60/523

Abstract: An FPC board includes a base insulating layer made of polyimide, for example. A conductor layer made of copper, for example, is formed on one surface of the base insulating layer. The conductor layer is composed of a pair of rectangular collector portions and extraction conductor portions extending in long-sized shapes from the collector portions. A coating layer is formed on the base insulating layer so as to coat the conductor layer. The coating layer is formed so as to coat the collector portions and the extraction conductor portions of the conductor layer. The coating layer is made of a resin composition containing carbon.

Abstract translation: FPC基板包括例如由聚酰亚胺制成的基底绝缘层。 例如，由铜制的导体层形成在基极绝缘层的一个表面上。 导体层由一对矩形集电体部分和从集电部分以大尺寸形状延伸的引出导体部分组成。 在基底绝缘层上形成涂层以涂覆导体层。 涂层形成为涂覆导体层的集电体部分和提取导体部分。 涂层由含有碳的树脂组合物制成。

公开(公告)号：US20080235941A1

公开(公告)日：2008-10-02

申请号：US11694913

申请日：2007-03-30

Applicant: Seng Guan Chow

Inventor： Seng Guan Chow

IPC: H05K3/34

CPC classification number: H05K3/284 ,  H01L2224/32225 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/19105 ,  H05K1/111 ,  H05K3/1216 ,  H05K3/3442 ,  H05K3/3452 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4007 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09072 ,  H05K2201/10636 ,  H05K2201/10992 ,  H05K2203/043 ,  H05K2203/1476 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49144 ,  H01L2924/00

Abstract: An integrated circuit package system is provided including providing a substrate having a contact pad, forming a first conductor having a first melting point over the contact pad, forming a second conductor having a second melting point over the first conductor with the first melting point higher than the second melting point, and mounting a first device over the second conductor.

Abstract translation: 提供了一种集成电路封装系统，包括提供具有接触焊盘的衬底，形成在接触焊盘上具有第一熔点的第一导体，在第一导体上形成具有第二熔点的第二导体，第一熔点高于 第二熔点，并且将第一装置安装在第二导体上。

公开(公告)号：US07417318B2

公开(公告)日：2008-08-26

申请号：US10831229

申请日：2004-04-26

Applicant: Tohru Nomura ,  Yoshihiro Shimoide ,  Yoshihiko Shiraishi ,  Rikiya Kamimura ,  Hiroshi Kasugai

Inventor： Tohru Nomura ,  Yoshihiro Shimoide ,  Yoshihiko Shiraishi ,  Rikiya Kamimura ,  Hiroshi Kasugai

IPC: H01L23/48

CPC classification number: H05K3/4061 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H05K1/092 ,  H05K3/248 ,  H05K2201/035 ,  H05K2201/09981 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A thick film circuit board that can be produced at a low cost, a method of producing the same, and an integrated circuit device. A first thick film circuit board has conducting layers of a copper-containing conductor fired at not higher than 750° C., and includes conducting portions formed by using a silver-containing conductor. A second thick film circuit board has conductors that are formed in the through holes so as to close the openings of at least the one side thereof. The thick film circuit board is produced at a low cost and suppresses a drop in electric conductivity when it is in use.

Abstract translation: 可以低成本制造的厚膜电路板，其制造方法和集成电路器件。 第一厚膜电路板具有在不高于750℃下烧制的含铜导体的导电层，并且包括通过使用含银导体形成的导电部分。 第二厚膜电路板具有形成在通孔中的导体，以便至少封闭其一侧的开口。 以低成本生产厚膜电路板，并且在使用时抑制电导率的降低。

公开(公告)号：US20080135283A1

公开(公告)日：2008-06-12

申请号：US11883801

申请日：2006-04-14

Applicant: Kunio Hibino ,  Yoshihiro Tomura ,  Yoshihiko Yagi ,  Kazuhiro Nishikawa

Inventor： Kunio Hibino ,  Yoshihiro Tomura ,  Yoshihiko Yagi ,  Kazuhiro Nishikawa

IPC: H05K3/30 ,  H01B5/00 ,  H05K1/18 ,  B29C39/10

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/11901 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13113 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/207 ,  H05K3/245 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2203/0113 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A protruding electrodes is formed on a lead electrode of an electronic component, and the protruding electrodes comprises a first conductor formed on the lead electrode of the electronic component, and a second conductor overlaid on the first conductor by using a transfer mold having a concavity. By virtue of this structure, protruding electrodes of any configuration can be formed in fine pitches.

Abstract translation: 在电子部件的引线电极上形成突起电极，突出电极包括形成在电子部件的引线电极上的第一导体和通过使用具有凹度的转移模具覆盖在第一导体上的第二导体。 通过这种结构，可以以细间距形成任何构造的突出电极。

公开(公告)号：US07381902B2

公开(公告)日：2008-06-03

申请号：US10951620

申请日：2004-09-29

Applicant: Norihito Tsukahara ,  Kazuhiro Nishikawa

Inventor： Norihito Tsukahara ,  Kazuhiro Nishikawa

IPC: H05K1/09

CPC classification number: H05K3/249 ,  H05K1/095 ,  H05K3/207 ,  H05K2201/035

Abstract: A wiring board comprises a patterned wiring formed of electrically conductive resin composed primarily of silver and embedded into a substrate in a manner that a surface thereof is exposed above the substrate, and a covering conductor formed primarily of carbon covering the surface of the patterned wiring. The wiring board of this structure is superior in resistance to moisture absorption and water, prevents silver migration attributable to the moisture, and reduces contact resistance in the connection between a terminal portion of the wiring board and an external apparatus.

Abstract translation: 布线板包括由主要由银构成并以其表面暴露在基板上方的方式嵌入到基板中的导电树脂形成的图案布线，以及主要由覆盖图案化布线表面的碳形成的覆盖导体。 该结构的布线基板具有优异的耐吸湿性和防水性，防止由于水分引起的银迁移，并且降低了布线板的端子部分与外部设备之间的连接中的接触电阻。

公开(公告)号：US20080110020A1

公开(公告)日：2008-05-15

申请号：US11558615

申请日：2006-11-10

Applicant: Peter T. Heisen ,  Scott A. Raby

Inventor： Peter T. Heisen ,  Scott A. Raby

IPC: H05K3/10 ,  H05K3/02

CPC classification number: H05K1/028 ,  H05K1/0218 ,  H05K1/095 ,  H05K3/247 ,  H05K2201/035 ,  H05K2201/0715 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49135 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: The invention removes copper from the concave side of a flex circuit around a bendable region and replaces it with a conductive epoxy to allow it to be formed to tighter bend radii than would otherwise be possible. After the flex circuit is shaped in a tight radius and attached to a mechanical structure, the conductive epoxy is cured to act as functional replacement of the removed copper.

Abstract translation: 本发明从可弯曲区域周围的柔性电路的凹面侧去除铜，并用导电环氧树脂替代它，以使其形成得比其它可能的弯曲半径更紧。 在柔性电路成形为紧密半径并连接到机械结构之后，导电环氧树脂被固化以用作去除的铜的功能性替代。

公开(公告)号：US07317610B2

公开(公告)日：2008-01-08

申请号：US11272781

申请日：2005-11-15

Applicant: Hirofumi Nakamura ,  Yutaka Akimoto ,  Sadamu Toita ,  Takayuki Inoi ,  Katsuhiro Yoshida

Inventor： Hirofumi Nakamura ,  Yutaka Akimoto ,  Sadamu Toita ,  Takayuki Inoi ,  Katsuhiro Yoshida

IPC: H01G4/228 ,  H01G9/00 ,  H01G9/04

CPC classification number: H01G9/025 ,  H01G9/15 ,  H05K1/162 ,  H05K2201/0329 ,  H05K2201/0347 ,  H05K2201/035 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2203/0315 ,  Y10T29/417

Abstract: A sheet-shaped capacitor for storing electrical charges of large capacities, and to assure facilitated manufacture, cost reduction and improved reliability, and a method for manufacturing the capacitor. The capacitor includes a dielectric film 12, formed on a first major surface of a metal plate 11, an electrically conductive high polymer layer 13, formed on a first major surface of the dielectric film, and an electrically conductive layer 14 formed on a first major surface of the electrically conductive high polymer layer 13, such as by copper plating. A cathode electrode 20 is led out from the electrically conductive layer 14 on the side electrically conductive high polymer layer 13.

Abstract translation: 一种用于存储大容量的电荷并且确保便于制造，降低成本和提高可靠性的片状电容器以及用于制造电容器的方法。 电容器包括形成在金属板11的第一主表面上的电介质膜12，形成在电介质膜的第一主表面上的导电高分子层13和形成在第一主体上的导电层14 导电高分子层13的表面，例如通过镀铜。 在导电性高分子层13的导电层14上引出阴极电极20。

公开(公告)号：US20070281099A1

公开(公告)日：2007-12-06

申请号：US11443265

申请日：2006-05-31

Applicant: James J. Howarth ,  Anthony R. James ,  Karel Vanheusden

Inventor： James J. Howarth ,  Anthony R. James ,  Karel Vanheusden

IPC: B05D1/12 ,  B05D3/02 ,  B05D7/00 ,  B05C5/00 ,  B41J2/01

CPC classification number: H05K3/247 ,  H05K1/095 ,  H05K3/125 ,  H05K2201/0257 ,  H05K2201/035 ,  H05K2203/013 ,  H05K2203/1476

Abstract: A system and a method are provided for ink-jet printing a solderable conductive pad onto a substrate. The system comprises at least one print head and a curing station for curing an ink deposited onto the substrate. The system is configured to: deposit at least a first layer of a first ink onto the substrate; cure the first layer of the first ink; deposit at least an intermediate layer of a second ink on top of the cured first layer of the first ink; cure the intermediate layer of the second ink; deposit at least a last layer of the first ink on top of the cured intermediate layer of the second ink; and cure the last layer of the first ink. The first ink has a relatively high conductivity. The second ink has a relatively low conductivity. The first layer, the intermediate layer, and the last layer may be arranged such that when solder is applied to the last layer, the solder is prevented from leaching through to the first layer.

Abstract translation: 提供了一种系统和方法，用于将可焊接导电垫喷墨印刷到基底上。 该系统包括至少一个打印头和固化站，用于固化沉积到基底上的油墨。 该系统被配置为：将至少第一层第一油墨沉积到基底上; 固化第一层油墨的第一层; 在第一墨水的固化的第一层的顶部上沉积至少第二墨水的中间层; 固化第二墨水的中间层; 在第二墨水的固化中间层的顶部上沉积至少最后一层第一墨; 并固化第一个墨水的最后一层。 第一种墨水具有较高的导电性。 第二墨水具有较低的导电性。 可以将第一层，中间层和最后一层布置成使得当将焊料施加到最后一层时，防止焊料浸入第一层。

公开(公告)号：US07288437B2

公开(公告)日：2007-10-30

申请号：US11048767

申请日：2005-02-03

Applicant: Akira Mase

Inventor： Akira Mase

IPC: H01L21/00

CPC classification number: G02F1/13452 ,  G02F1/13439 ,  G02F1/1345 ,  H01L21/4867 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81192 ,  H01L2224/83851 ,  H01L2924/00011 ,  H05K1/095 ,  H05K3/245 ,  H05K2201/0326 ,  H05K2201/035 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49155 ,  H01L2224/29075 ,  H01L2924/00014

Abstract: An improved method of forming an electrode pattern on a substrate is described. The substrate is coated with a first conductive film and subjected to baking. On the first conductive film is then overlied a second conductive film which mends possible fissures of the first conductive film which, besides, would produce open circuits in the pattern.

Abstract translation: 描述了在衬底上形成电极图案的改进方法。 将基板涂覆有第一导电膜并进行烘烤。 然后在第一导电膜上覆盖第二导电膜，该第二导电膜补偿第一导电膜的可能的裂缝，此外，该图案将产生图案中的开路。