Printed wiring board
    21.
    发明授权
    Printed wiring board 有权
    印刷电路板

    公开(公告)号:US08664534B2

    公开(公告)日:2014-03-04

    申请号:US11915097

    申请日:2006-05-19

    Abstract: It is an object of the present invention to provide a printed circuit board that can be housed at high density in the enclosures of electronic devices. The printed circuit board (40) according to a preferred embodiment of the invention has a construction with a substrate (1), a conductor (7) formed in a flexible region (36) and conductors (8,9) formed in non-flexible regions (46). The conductor (7) formed in the flexible region (36) has a total thickness of 1-30 μm, and the conductors (8,9) formed in the non-flexible regions (46) have a total thickness of 30-150 μm.

    Abstract translation: 本发明的目的是提供一种能够以高密度容纳在电子设备的外壳中的印刷电路板。 根据本发明的优选实施例的印刷电路板(40)具有基底(1),形成在柔性区域(36)中的导体(7)和形成为非柔性的导体(8,9)的结构 地区(46)。 形成在柔性区域(36)中的导体(7)具有1-30μm的总厚度,并且形成在非柔性区域(46)中的导体(8,9)的总厚度为30-150μm 。

    PRINTED CIRCUIT BOARD AND METHOD OF FABRICATING THE SAME
    22.
    发明申请
    PRINTED CIRCUIT BOARD AND METHOD OF FABRICATING THE SAME 审中-公开
    印刷电路板及其制造方法

    公开(公告)号:US20140000952A1

    公开(公告)日:2014-01-02

    申请号:US13921128

    申请日:2013-06-18

    Inventor: Young Gwan KO

    Abstract: Disclosed is a printed circuit board, which includes an insulating member having a circuit pattern embedded in one surface thereof, a bump pad formed in the insulating member so as to be connected to the circuit pattern and protruding from an outer surface of the insulating member, a build-up layer formed on one surface of the insulating member and including a build-up insulating layer and a circuit layer formed in the build-up insulating layer and having a via connected to the circuit pattern, and a solder resist layer formed on the build-up layer. A method of fabricating the printed circuit board is also provided. The printed circuit board is fabricated using a build-up process and the outermost circuit layer thereof is formed to have an embedded structure using an imprinting process, thus minimizing the separation of the circuit layer and reducing the lead time and the fabrication cost.

    Abstract translation: 公开了一种印刷电路板,其包括具有嵌入其一个表面中的电路图案的绝缘构件,形成在所述绝缘构件中以与所述电路图案连接并从所述绝缘构件的外表面突出的凸块焊盘, 形成在所述绝缘构件的一个表面上并包括积聚绝缘层和形成在所述积层绝缘层中并且具有连接到所述电路图案的通孔的电路层的堆积层,以及形成在所述绝缘层上的阻焊层 积层。 还提供了制造印刷电路板的方法。 印刷电路板使用积聚工艺制造,并且其最外面的电路层被形成为具有使用压印工艺的嵌入式结构,从而最小化电路层的分离并减少了交货时间和制造成本。

    CIRCUIT BOARD WITH HIGHER CURRENT
    26.
    发明申请
    CIRCUIT BOARD WITH HIGHER CURRENT 失效
    具有较高电流的电路板

    公开(公告)号:US20130050968A1

    公开(公告)日:2013-02-28

    申请号:US13304415

    申请日:2011-11-25

    Abstract: A circuit board includes a plurality of conductive layers, at least one group of vias, a number of second vias, at least one power supply element, and at least one electronic element. Each conductive layer includes a conductive portion. Both the first vias and the second vias are defined through the conductive layers and electrically connected each conductive layers. The at least one group of first vias surrounds the at least one power supply element. The second vias are arranged along the side of the conductive portion, and positioned between the power supply element and the electronic element. Current from a power supply element flows to the inner conductive layers through the group of surrounding first vias. Current transmission on each conductive layer continuously flows to another conductive layer having a lower resistance through the second vias during transmission.

    Abstract translation: 电路板包括多个导电层,至少一组通孔,多个第二通孔,至少一个电源元件和至少一个电子元件。 每个导电层包括导电部分。 第一通孔和第二通孔都通过导电层定义并电连接每个导电层。 所述至少一组第一通孔围绕所述至少一个电源元件。 第二通孔沿着导电部分的侧面布置,并且位于电源元件和电子元件之间。 来自电源元件的电流通过一组周围的第一通孔流到内部导电层。 在传输期间,每个导电层上的电流传输通过第二通孔连续流动到具有较低电阻的另一导电层。

    Multilayered printed wiring board
    27.
    发明授权
    Multilayered printed wiring board 有权
    多层印刷线路板

    公开(公告)号:US08367943B2

    公开(公告)日:2013-02-05

    申请号:US11831389

    申请日:2007-07-31

    Abstract: A multilayered printed wiring board has a core substrate having a through hole opening with a radius R, a through hole structure formed at the through hole opening and including a lid-shaped conductive structure, a first interlaminar resin insulation layer formed over the core substrate and having a first via hole structure with a bottom radius r, and a second interlaminar resin insulation layer formed over the first interlaminar resin insulation layer and having a second via hole structure. The lid-shaped conductive structure is formed over the core substrate at an end portion of the through-hole opening and covering the end portion of the through-hole opening. The first via hole structure is formed on the lid-shaped conductive structure and has an electroless plated film and an electrolytic plated film. The second via hole structure has an electroless plated film and an electrolytic plated film. The first via hole has a gravity center at or beyond a radius D, where D=(R−r/3) and the radius D is measured from a gravity center of the through-hole opening, and the bottom radius r of the first via hole is larger than a bottom radius of the second via hole.

    Abstract translation: 多层印刷布线板具有芯基板,其具有半径为R的通孔开口,通孔结构形成在通孔开口处并且包括盖形导电结构,形成在芯基板上的第一层间树脂绝缘层和 具有底部半径r的第一通孔结构和形成在第一层间树脂绝缘层上并具有第二通孔结构的第二层间树脂绝缘层。 盖形导电结构在通孔开口的端部处形成在芯基板上,并且覆盖通孔开口的端部。 第一通孔结构形成在盖状导电结构上,并具有无电镀膜和电解电镀膜。 第二通孔结构具有无电解电镀膜和电解电镀膜。 第一通孔具有重心在半径D以上或超过半径D,其中D =(R-r / 3),并且半径D从通孔开口的重心测量,并且第一通孔的底部半径r 通孔大于第二通孔的底部半径。

    Multilayer printed wiring board
    29.
    发明授权
    Multilayer printed wiring board 有权
    多层印刷线路板

    公开(公告)号:US08334466B2

    公开(公告)日:2012-12-18

    申请号:US12842431

    申请日:2010-07-23

    Applicant: Takashi Kariya

    Inventor: Takashi Kariya

    Abstract: A multilayer printed wiring board including a core substrate, a built-up wiring layer having a first surface in contact with the substrate and a second surface, the second surface including a mounting area for mounting a semiconductor device, the built-up layer including circuits and insulating layers, first through-hole conductors formed in a first portion of the substrate which corresponds to the mounting area, second through-hole conductors formed in a second portion of the substrate which corresponds to an area of the second surface other than the mounting area, third through-hole conductors formed in a processor core area of the first portion of the substrate which corresponds to a processor core section of the device, and pads provided on the second surface. The first conductors have a pitch smaller than a pitch of the second conductors, and the third conductors have a pitch smaller than the pitch of the first conductors.

    Abstract translation: 一种多层印刷电路板,包括芯基板,具有与基板接触的第一表面的积层布线层和第二表面,所述第二表面包括用于安装半导体器件的安装区域,所述堆叠层包括电路 和绝缘层,形成在所述基板的与所述安装区域对应的第一部分中的第一通孔导体,形成在所述基板的第二部分中的第二通孔导体,所述第二通孔导体对应于所述第二表面的除了所述安装 形成在基板的第一部分的处理器核心区域中的区域,第三通孔导体,其对应于设备的处理器核心部分,以及焊盘,设置在第二表面上。 第一导体的间距小于第二导体的间距,第三导体的间距小于第一导体的间距。

    Printed circuit board
    30.
    发明授权
    Printed circuit board 有权
    印刷电路板

    公开(公告)号:US08330047B2

    公开(公告)日:2012-12-11

    申请号:US12409544

    申请日:2009-03-24

    Abstract: A first insulating layer is formed on a suspension body and a wiring trace is formed on the first insulating layer. In addition, a ground trace is formed on the first insulating layer so as to extend along the wiring trace on one side of the wiring trace with a spacing therebetween. A second insulating layer is formed on the first insulating layer to cover the wiring trace and the ground trace. On the second insulating layer, a wiring trace is formed at a position above the wiring trace. A third insulating layer is formed on the second insulating layer to cover the wiring trace. The width of the wiring trace is set larger than the width of the wiring trace. At least a partial region of the ground trace and at least a partial region of the wiring trace are opposite to each other with part of the second insulating layer sandwiched therebetween.

    Abstract translation: 在悬架体上形成第一绝缘层,在第一绝缘层上形成布线。 此外,在第一绝缘层上形成接地迹线,以沿着布线迹线的一侧的布线迹线间隔开间隔延伸。 在第一绝缘层上形成第二绝缘层以覆盖布线迹线和接地迹线。 在第二绝缘层上,在布线迹线上方的位置形成布线。 在第二绝缘层上形成第三绝缘层以覆盖布线迹线。 布线迹线的宽度设置为大于布线迹线的宽度。 所述接地轨迹的至少部分区域和所述布线轨迹的至少部分区域彼此相对,并且夹在其间的所述第二绝缘层的一部分。

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