公开(公告)号：US20160157340A1

公开(公告)日：2016-06-02

申请号：US15019473

申请日：2016-02-09

Applicant: Dyi-Chung HU

Inventor： Dyi-Chung HU

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/11

CPC classification number: H05K1/119 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/111 ,  H05K1/115 ,  H05K3/107 ,  H05K3/244 ,  H05K2201/0347 ,  H05K2201/0376 ,  Y02P70/611 ,  Y10T29/49002

Abstract: A formation method of circuit board structure is disclosed. The formation method comprises: forming an intermediate substrate having interconnections therein and circuit patterns on both upper and lower surfaces, wherein the interconnections electrically connect the upper and lower circuit patterns; forming an upper dielectric layer overlying the upper circuit patterns, wherein the upper dielectric layer has a plurality of trenches therein; forming conductive wires in the trenches using e-less plating; and forming at least one protective layer overlying the conductive wires using a surface finishing process. The circuit board structure features formation of embedded conductive wires in the dielectric layer so that a short circuit can be avoid.

Abstract translation: 公开了一种电路板结构的形成方法。 形成方法包括：在其中形成具有互连的中间衬底和上表面和下表面上的电路图案，其中互连电连接上电路图案和下电路图案; 形成覆盖上层电路图案的上介电层，其中上电介质层中具有多个沟槽; 使用无电镀在沟槽中形成导线; 以及使用表面精加工方法形成覆盖在导线上的至少一个保护层。 电路板结构特征在于在电介质层中形成嵌入的导线，从而可以避免短路。

公开(公告)号：US20160155716A1

公开(公告)日：2016-06-02

申请号：US14837245

申请日：2015-08-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ming-Chen Sun ,  Chun-Hsien Lin ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Yu-Cheng Pai

IPC: H01L23/00 ,  H01L21/56 ,  H05K3/00 ,  H05K3/10 ,  H05K3/40 ,  H01L23/31 ,  H05K1/11

CPC classification number: H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2924/15313 ,  H05K1/111 ,  H05K3/20 ,  H05K3/205 ,  H05K3/428 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

Abstract translation: 提供封装基板和半导体封装。 封装衬底包括具有相对的第一和第二表面的绝缘层; 形成在绝缘层中的第一布线层，从绝缘层的第一表面露出并具有多个第一导电焊盘; 形成在所述绝缘层中的第二布线层，从所述第二表面露出并具有多个第二导电焊盘; 第三布线层，形成在第一表面上并与第一布线层电连接; 形成在所述第一导电焊盘上的多个第一金属凸块对应; 以及垂直嵌入绝缘层中并与第二和第三布线层电连接的至少一个导电通孔。 因此，第一导电焊盘的表面被减小，并且避免了第一导电焊盘和形成在导电凸块上的焊料材料之间的不润湿。

公开(公告)号：US09307651B2

公开(公告)日：2016-04-05

申请号：US13421330

申请日：2012-03-15

Applicant: Tsung-Yuan Chen ,  Shu-Sheng Chiang

Inventor： Tsung-Yuan Chen ,  Shu-Sheng Chiang

IPC: H01K3/10 ,  H05K3/10 ,  H05K3/04 ,  H05K3/42

CPC classification number: H05K3/107 ,  H05K3/045 ,  H05K3/423 ,  H05K3/426 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09563 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A fabricating process for an embedded circuit structure is provided. A through hole is formed in a core panel and penetrates the core panel. Two indent patterns are respectively formed on two opposite surfaces of the core panel. A conductive material is electroplated into the through hole and the indent patterns, so as to form a conductive channel in the through hole and two circuit patterns in the indent patterns respectively. Portions of the circuit patterns, which exceed the indent patterns respectively, are removed for planarizing the circuit patterns to be level with the two surfaces of the core panel respectively.

Abstract translation: 提供了一种用于嵌入式电路结构的制造工艺。 在芯板中形成贯通孔，贯通芯板。 在芯板的两个相对的表面上分别形成两个压痕图案。 将导电材料电镀到通孔和凹陷图案中，以在通孔中分别形成导电通道和凹陷图案中的两个电路图案。 电路图案的分别超过凹口图案的部分被去除，用于将电路图案平坦化以与芯板的两个表面分级。

公开(公告)号：US20160044782A1

公开(公告)日：2016-02-11

申请号：US14919058

申请日：2015-10-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshihito Otsubo ,  Toru Meguro ,  Tatsunori Kan

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/09 ,  H01L21/4867 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/19105 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/115 ,  H05K3/0058 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4084 ,  H05K3/42 ,  H05K3/4629 ,  H05K3/4644 ,  H05K3/4667 ,  H05K2201/0376 ,  H05K2201/0382 ,  H05K2201/09545 ,  H05K2201/09627 ,  H05K2201/09836 ,  H05K2201/09845 ,  H05K2201/1006 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/068 ,  H05K2203/1126 ,  H01L2924/00

Abstract: A multilayer wiring substrate that can realize a higher-density wiring structure is obtained. Provided is a multilayer wiring substrate, where a multilayer body including a first insulating layer and a second insulating layer stacked on the bottom surface of the first insulating layer includes printed wiring electrodes; the printed wiring electrodes are formed by printing with and sintering conductive paste; the printed wiring electrodes respectively include first wiring electrode portions located on the second insulating layer and second wiring electrode portions respectively joined to first wiring electrode portions; and the second wiring electrode portions respectively extend into through holes and, further, are exposed at the top surface of the first insulating layer.

Abstract translation: 可以获得能够实现更高密度的布线结构的多层布线基板。 提供了一种多层布线基板，其中堆叠在第一绝缘层的底表面上的包括第一绝缘层和第二绝缘层的多层体包括印刷布线电极; 印刷布线电极通过印刷和烧结导电浆料形成; 印刷布线电极分别包括位于第二绝缘层上的第一布线电极部分和分别连接到第一布线电极部分的第二布线电极部分; 并且第二布线电极部分别分别延伸到通孔中，并且还暴露在第一绝缘层的顶表面处。

公开(公告)号：US09204546B2

公开(公告)日：2015-12-01

申请号：US14181739

申请日：2014-02-17

Applicant: Chin-Sheng Wang ,  Ching-Sheng Chen ,  Chun-Kai Lin ,  Chao-Min Wang

Inventor： Chin-Sheng Wang ,  Ching-Sheng Chen ,  Chun-Kai Lin ,  Chao-Min Wang

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/00

CPC classification number: H05K1/113 ,  H05K1/115 ,  H05K3/0097 ,  H05K3/4007 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/1536 ,  H05K2203/1563 ,  Y10T29/49165

Abstract: A circuit board includes a circuit layer, a first solder resist layer, a second solder resist layer and at least one conductive bump. The first solder resist layer is disposed on a lower surface of the circuit layer and has at least one first opening exposing a portion of the lower surface of the circuit layer. The second solder resist layer is disposed on an upper surface of the circuit layer and has at least one second opening exposing a portion of the upper surface of the circuit layer. The conductive bump is disposed inside the second opening of the second solder resist layer and directly connects to the upper surface of the circuit layer exposed by the second opening. A top surface of the conductive bump is higher than a second surface of the second solder resist layer.

Abstract translation: 电路板包括电路层，第一阻焊层，第二阻焊层和至少一个导电凸块。 第一阻焊层设置在电路层的下表面上，并且具有暴露电路层的下表面的一部分的至少一个第一开口。 第二阻焊层设置在电路层的上表面上，并且具有暴露电路层的上表面的一部分的至少一个第二开口。 导电凸块设置在第二阻焊层的第二开口内，并且直接连接到由第二开口暴露的电路层的上表面。 导电凸块的顶表面高于第二阻焊层的第二表面。

公开(公告)号：US20150327355A1

公开(公告)日：2015-11-12

申请号：US14443231

申请日：2013-11-15

Applicant: JUMATECH GMBH

Inventor： Markus WÖLFEL

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/11

CPC classification number: H05K1/028 ,  H05K1/0265 ,  H05K1/0278 ,  H05K1/111 ,  H05K3/0014 ,  H05K3/0017 ,  H05K3/202 ,  H05K2201/0275 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/057 ,  H05K2201/09027 ,  H05K2201/0969 ,  H05K2201/1028 ,  Y10T29/49156

Abstract: An angle-adjustable printed circuit board structure having two printed circuit board sections arranged angularly with respect to one another. The printed circuit board structure contains at least one conduction element which is embedded at least predominantly in the printed circuit board structure and which extends between two contact pads and is electrically conductively connected to said contact pads. The two contact pads are situated on different printed circuit board sections. The printed circuit board sections are angle-adjustable and/or angled relative to one another with maintenance of the connections between the contact pads and the at least one conduction element and with bending of the at least one conduction element via a bending edge between the printed circuit board sections. The conduction element has a larger extent along the bending edge than perpendicularly thereto, as viewed in cross section.

Abstract translation: 一种角度可调的印刷电路板结构，其具有相对于彼此成角度地布置的两个印刷电路板部分。 印刷电路板结构包含至少一个导电元件，其至少主要嵌入在印刷电路板结构中，并且在两个接触焊盘之间延伸并且导电地连接到所述接触焊盘。 两个接触垫位于不同的印刷电路板部分上。 印刷电路板部分可相对于彼此具有角度可调节和/或成角度，同时维持接触焊盘和至少一个传导元件之间的连接，并且通过经印刷的弯曲边缘弯曲至少一个导电元件 电路板部分。 如横截面所示，导电元件沿着弯曲边缘比垂直方向具有更大的程度。

公开(公告)号：US20150313008A1

公开(公告)日：2015-10-29

申请号：US14261465

申请日：2014-04-25

Applicant: Todd Mathew Spath ,  Ronald Steven Cok

Inventor： Todd Mathew Spath ,  Ronald Steven Cok

IPC: H05K1/02 ,  G06F3/044 ,  H05K1/09 ,  G06F3/041

CPC classification number: H05K1/097 ,  G06F3/047 ,  G06F2203/04103 ,  G06F2203/04112 ,  H05K1/189 ,  H05K3/1258 ,  H05K3/247 ,  H05K2201/0108 ,  H05K2201/0329 ,  H05K2201/0338 ,  H05K2201/035 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/1545

Abstract: A multi-layer micro-wire structure resistant to cracking including a substrate having a surface, one or more micro-channels formed in the substrate, an electrically conductive first material composition forming a first layer located in each micro-channel, and an electrically conductive second material composition having a greater tensile ductility than the first material composition forming a second layer located in each micro-channel, the first material composition and the second material composition in electrical contact to form an electrically conductive multi-layer micro-wire in each micro-channel, whereby the multi-layer micro-wire is resistant to cracking

Abstract translation: 一种耐裂纹的多层微线结构，包括具有表面的基底，在基底中形成的一个或多个微通道，形成位于每个微通道中的第一层的导电第一材料组合物，以及导电 第二材料组合物具有比形成位于每个微通道中的第二层的第一材料组合物更大的拉伸延展性，第一材料组合物和第二材料组合物电接触以在每个微通道中形成导电多层微线 通道，由此多层微线耐开裂

公开(公告)号：US09153524B2

公开(公告)日：2015-10-06

申请号：US14320836

申请日：2014-07-01

Applicant: Koei Suzuki ,  Takanori Tano ,  Hiroshi Miura ,  Atsushi Onodera

Inventor： Koei Suzuki ,  Takanori Tano ,  Hiroshi Miura ,  Atsushi Onodera

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/288 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76879 ,  H01L27/124 ,  H01L27/1292 ,  H01L2924/0002 ,  H05K1/16 ,  H05K3/1208 ,  H05K3/1258 ,  H05K3/4664 ,  H05K2201/0376 ,  H05K2203/107 ,  H05K2203/1173 ,  H01L2924/00

Abstract: A method of forming a stacked-layer wiring includes forming first wettability variable layer on a substrate using material that changes surface energy by energy application; forming first conductive layer in or on the first wettability variable layer; forming second wettability variable layer on the first wettability variable layer using material that changes surface energy by energy application; forming concave portion to become wiring pattern of second conductive layer to the second wettability variable layer while concurrently forming high surface energy area on surface exposed by forming the concave portion by changing surface energy; forming via hole by exposing a part of the first conductive layer while concurrently forming high surface energy area on surface exposed by forming the via hole by changing surface energy; and applying conductive ink to the high surface energy area to form the second conductive layer and via simultaneously.

Abstract translation: 形成堆叠层布线的方法包括：使用通过能量施加而改变表面能的材料在基板上形成第一润湿性变化层; 在第一润湿性变化层中或上面形成第一导电层; 使用通过能量施加改变表面能的材料在第一润湿性变化层上形成第二润湿性变化层; 形成凹部以成为第二导电层的布线图案到第二可润湿性变化层，同时通过改变表面能而形成凹部而露出的表面上形成高表面能区域; 通过暴露第一导电层的一部分而形成通孔，同时通过通过改变表面能形成通孔而在暴露的表面上形成高表面能区域; 以及将导电油墨施加到高表面能区域以形成第二导电层并同时通过。

公开(公告)号：US20150282333A1

公开(公告)日：2015-10-01

申请号：US14225682

申请日：2014-03-26

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yu-Te Lu

IPC: H05K3/46 ,  H05K3/34 ,  H05K3/28 ,  H05K3/00 ,  H05K3/10

CPC classification number: H05K3/4611 ,  H05K3/0094 ,  H05K3/10 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/421 ,  H05K3/4658 ,  H05K2201/0376 ,  H05K2203/06 ,  H05K2203/0723 ,  H05K2203/143

Abstract: A method of manufacturing a multilayer substrate structure includes the steps of pre-treatment, pressing and post-treatment. A carrier plate provided with a circuit pattern layer is pressed against a plastic sheet. An interlayer connection pad is formed by drilling and filling the lower surface of the plastic sheet. The carrier plate, the plastic sheet, another plastic sheet and another carrier plate with a circuit pattern layer are pressed together, and then drilled/filled to form a multilayer stacked structure such that the two circuit pattern layers are indirectly and electrically connected to the interlayer connection pad, respectively. Therefore, it is possible to overcome the problem due to alignment tolerance by using the interlayer connection pad wider than alignment tolerance, and stacking the circuit layers, each having much finer line and smaller pitch.

Abstract translation: 制造多层基板结构的方法包括预处理，压制和后处理的步骤。 设置有电路图案层的承载板被压靠在塑料片上。 通过钻孔和填充塑料片的下表面形成夹层连接垫。 将载板，塑料片，另一塑料片和具有电路图案层的另一载体板压在一起，然后钻孔/填充以形成多层堆叠结构，使得两个电路图案层间接地并电连接到中间层 连接垫。 因此，可以通过使用比对准公差宽的层间连接焊盘来克服由于对准公差引起的问题，并且堆叠各个具有更细的线和更小间距的电路层。

公开(公告)号：US20150268770A1

公开(公告)日：2015-09-24

申请号：US14217544

申请日：2014-03-18

Applicant: RONALD STEVEN COK

Inventor： RONALD STEVEN COK

IPC: G06F3/047 ,  H05K1/09 ,  H05K1/02

CPC classification number: G06F3/047 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04112 ,  H01L29/413 ,  H01L33/42 ,  H01L51/5215 ,  H05K1/0289 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/117 ,  H05K3/465 ,  H05K3/4664 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09845 ,  H05K2201/10128 ,  Y10T29/49155

Abstract: A multi-layer micro-wire structure includes first and second substrates having first and second layers extending to first and second layer edges, respectively. The first layer includes first micro-wire electrodes and first connection pads. Each first micro-wire electrode includes one or more electrically connected first micro-wires and each first connection pad electrically connects to a corresponding first micro-wire electrode. The second layer includes second micro-wire electrodes and second connection pads. Each second micro-wire electrode includes one or more electrically connected second micro-wires, and each second connection pad electrically connects to a corresponding second micro-wire electrode. The second layer is located between the first substrate and the second substrate and the second layer edge extends at least partly beyond the first layer edge so that one or more of the second connection pads is located between at least a portion of the first layer edge and the second layer edge.

Abstract translation: 多层微线结构包括分别具有延伸到第一和第二层边缘的第一和第二层的第一和第二基底。 第一层包括第一微线电极和第一连接焊盘。 每个第一微线电极包括一个或多个电连接的第一微线，并且每个第一连接焊盘电连接到对应的第一微线电极。 第二层包括第二微线电极和第二连接焊盘。 每个第二微线电极包括一个或多个电连接的第二微线，并且每个第二连接焊盘电连接到对应的第二微线电极。 第二层位于第一衬底和第二衬底之间，并且第二层边缘至少部分地延伸超过第一层边缘，使得一个或多个第二连接焊盘位于第一层边缘的至少一部分和 第二层边缘。