公开(公告)号：US09204538B2

公开(公告)日：2015-12-01

申请号：US13968804

申请日：2013-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Ying Lee ,  Jyu-Horng Shieh

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L23/5283 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L2924/0002 ,  H05K1/0296 ,  H05K1/11 ,  H05K3/002 ,  H05K2201/09236 ,  H01L2924/00

Abstract: A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.

Abstract translation: 一种方法包括在基材上形成硬掩模，并在硬掩模中形成I形的第一开口。 第一开口包括两个平行部分和连接两个平行部分的连接部分。 间隔件形成在第一开口的侧壁上。 间隔件填充整个连接部分，其中两个平行部分中的每一个的中心部分未被间隔件填充。 蚀刻硬掩模以去除硬掩模的一部分并形成第二开口，其中第二开口位于第一开口的两个平行部分之间。 第二开口通过间隔件与第一开口的两个平行部分间隔开。 然后将第一开口和第二开口向下延伸到基底材料中。

公开(公告)号：US20150319847A1

公开(公告)日：2015-11-05

申请号：US14689478

申请日：2015-04-17

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Seong Yeon KIM ,  Hong In KIM

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0245 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/0224 ,  H05K1/115 ,  H05K2201/09236

Abstract: A wiring substrate may include an insulating layer; a differential signal transmission line including a first wiring formed on a first surface of the insulating layer and a second wiring formed on a second surface of the insulating layer, the first wiring and the second wiring transmitting differential signals; and a ground part including a first ground layer and a second ground layer disposed to be spaced apart from the first wiring by the predetermined distance on the first surface of the insulating layer and a third ground layer and a fourth ground layer disposed to be spaced apart from the second wiring by the predetermined distance on the second surface of the insulating layer.

Abstract translation: 布线基板可以包括绝缘层; 差分信号传输线，包括形成在所述绝缘层的第一表面上的第一布线和形成在所述绝缘层的第二表面上的第二布线，所述第一布线和所述第二布线传输差分信号; 以及接地部，包括第一接地层和第二接地层，所述第一接地层和第二接地层设置成与所述绝缘层的所述第一表面上的所述第一布线间隔预定距离，以及设置成间隔开的第三接地层和第四接地层 从绝缘层的第二表面上的第二布线预定距离。

公开(公告)号：US09173284B2

公开(公告)日：2015-10-27

申请号：US14068029

申请日：2013-10-31

Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.

Inventor： Kuo-Fu Su ,  Gwun-Jin Lin

IPC: H05K1/00 ,  H05K1/02 ,  H01B7/08 ,  H05K3/28

CPC classification number: H05K1/024 ,  H01B7/0838 ,  H01B7/0861 ,  H05K1/0242 ,  H05K1/025 ,  H05K3/28 ,  H05K3/281 ,  H05K2201/0323 ,  H05K2201/09236 ,  H05K2201/098 ,  H05K2201/09881

Abstract: A planarized cover layer structure of a flexible circuit board includes an insulation layer bonded through a first adhesive layer to a surface of each one of conductive signal lines laid on a substrate of a flexible circuit board. Separation areas respectively formed between adjacent ones of the conductive signal lines are each formed with a filling layer, so that the filling layer provides the first adhesive layer with a planarization height in the separation areas and the planarization height is substantially equal to the height of the conductive signal lines. The filling layer can alternatively be of a height that is higher than the surface of the conductor layer by a covering height so that the first adhesive layer has a planarization height in the separation areas and the planarization height is substantially equal to the sum of the height of the conductive signal lines and the covering height.

Abstract translation: 柔性电路板的平面化覆盖层结构包括通过第一粘合剂层粘合到布置在柔性电路板的基板上的每个导电信号线的表面的绝缘层。 分别在相邻的导电信号线之间形成的分离区域各自形成有填充层，使得填充层在分离区域中为第一粘合剂层提供平坦化高度，并且平坦化高度基本上等于 导电信号线。 填充层可以替代地具有比导体层的表面高一个覆盖高度的高度，使得第一粘合剂层在分离区域中具有平坦化高度，并且平坦化高度基本上等于高度 的导电信号线和覆盖高度。

公开(公告)号：US09131603B2

公开(公告)日：2015-09-08

申请号：US13844761

申请日：2013-03-15

Applicant: INTEL CORPORATION

Inventor： Kai Xiao ,  Jimmy Hsu ,  Yuan-Liang Li ,  Richard K. Kunze

IPC: H05K1/02 ,  H01P3/08 ,  H01P11/00

CPC classification number: H05K1/0228 ,  H01P3/08 ,  H01P11/00 ,  H05K1/0245 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09709 ,  Y10T29/49155

Abstract: A signal line design is described herein. A circuit board may include a first signal line and a second signal line. The first signal line includes a pair of signal lines at a first depth of a section of a circuit board, wherein a centerline extends lengthwise between the pair of signal lines. The second signal line is disposed at a second depth of the circuit board. The second signal line includes a first segment that runs parallel to the first signal line at a first displacement from the center line. The second signal line includes a second segment that runs parallel to the first signal line on the other side of the center line at a second displacement distance from the center line.

Abstract translation: 这里描述了信号线设计。 电路板可以包括第一信号线和第二信号线。 第一信号线包括在电路板的一部分的第一深度处的一对信号线，其中中心线在该对信号线之间纵向延伸。 第二信号线设置在电路板的第二深度处。 第二信号线包括第一段，该第一段在与中心线的第一位移处平行于第一信号线延伸。 第二信号线包括与中心线的另一侧平行于第一信号线的第二段，距中心线的第二位移距离。

公开(公告)号：US20150237722A1

公开(公告)日：2015-08-20

申请号：US14628189

申请日：2015-02-20

Applicant: Ruey-Jen Hwu ,  Jishi Ren ,  Laurence P. Sadwick

Inventor： Ruey-Jen Hwu ,  Jishi Ren ,  Laurence P. Sadwick

IPC: H05K1/02 ,  H01R43/20

CPC classification number: H05K1/024 ,  H01P3/082 ,  H01P3/084 ,  H05K2201/0187 ,  H05K2201/09236 ,  Y10T29/49204

Abstract: An anode array system includes a number of electrically conductive strips arranged in an array to form an anode, each of the plurality of electrically conductive strips having a first end and a second end, electrical connectors at the first end and at the second end of each of the electrically conductive strips, and a substrate at least partially supporting the electrically conductive strips, wherein the substrate is porous.

Abstract translation: 阳极阵列系统包括排列成阵列以形成阳极的多个导电条，多个导电条中的每一个具有第一端和第二端，在每个的第一端和第二端的电连接器 的导电条，以及至少部分地支撑导电条的基底，其中基底是多孔的。

公开(公告)号：US20150129284A1

公开(公告)日：2015-05-14

申请号：US14076667

申请日：2013-11-11

Applicant: Seagate Technology LLC

Inventor： Prapan Aparimarn ,  Chaovalit Chiyatan ,  Piriyakorn Jirawattanakasem ,  Joompondej Bamrungwongtaree

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/111 ,  G11B5/486 ,  H05K1/0296 ,  H05K1/056 ,  H05K1/11 ,  H05K3/3436 ,  H05K2201/09236 ,  H05K2201/09281 ,  H05K2201/09727 ,  Y02P70/611

Abstract: A printed circuit substrate may be configured with at least one internal lead designed and shaped to reduce solder bridging. The printed circuit substrate can have a plurality of internal leads that each has a continuously curvilinear boundary that defines an isolation channel. The isolation channel may be configured with a uniform distance that separates a first internal lead from an adjacent second internal lead.

Abstract translation: 印刷电路基板可以配置有至少一个设计和成形以减少焊料桥接的内部引线。 印刷电路基板可以具有多个内部引线，每个内部引线具有限定隔离通道的连续曲线边界。 隔离通道可以配置有将第一内部引线与相邻的第二内部引线分开的均匀距离。

公开(公告)号：US20150055307A1

公开(公告)日：2015-02-26

申请号：US13974569

申请日：2013-08-23

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： John Wayne Shaw ,  Jacob Charles Matousek ,  Todd Michael Lammers

IPC: H05K1/18

CPC classification number: H05K1/0253 ,  H05K1/0224 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/09681

Abstract: A rigid multi-layer printed circuit board (PCB) has an embedded elongated conductor between opposing first and second reference planes. The first and second reference planes are formed of conductive material and are electrically isolated from the conductor by intervening insulative material. Each of the first and second reference planes have a plurality of spaced apart windows extending therethrough, the windows aligned with the elongated conductor.

Abstract translation: 刚性多层印刷电路板（PCB）在相对的第一和第二参考平面之间具有嵌入​​的细长导体。 第一和第二参考平面由导电材料形成，并通过介入的绝缘材料与导体电隔离。 第一和第二参考平面中的每一个具有从其延伸穿过的多个间隔开的窗口，窗口与细长导体对准。

公开(公告)号：US20150036406A1

公开(公告)日：2015-02-05

申请号：US14519967

申请日：2014-10-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi BETSUI ,  Naoto TAOKA ,  Motoo SUWA ,  Shigezumi MATSUI ,  Norihiko SUGITA ,  Yoshiharu FUKUSHIMA

IPC: G11C5/02

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract translation: 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下，与仅在一侧具有存储器接口电路的半导体板相比，可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此，微型计算机在主板和模块板上简化了线路设计。

公开(公告)号：US20150027751A1

公开(公告)日：2015-01-29

申请号：US14068029

申请日：2013-10-31

Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.

Inventor： KUO-FU SU ,  GWUN-JIN LIN

IPC: H05K1/02

CPC classification number: H05K1/024 ,  H01B7/0838 ,  H01B7/0861 ,  H05K1/0242 ,  H05K1/025 ,  H05K3/28 ,  H05K3/281 ,  H05K2201/0323 ,  H05K2201/09236 ,  H05K2201/098 ,  H05K2201/09881

Abstract: A planarized cover layer structure of a flexible circuit board includes an insulation layer bonded through a first adhesive layer to a surface of each one of conductive signal lines laid on a substrate of a flexible circuit board. Separation areas respectively formed between adjacent ones of the conductive signal lines are each formed with a filling layer, so that the filling layer provides the first adhesive layer with a planarization height in the separation areas and the planarization height is substantially equal to the height of the conductive signal lines. The filling layer can alternatively be of a height that is higher than the surface of the conductor layer by a covering height so that the first adhesive layer has a planarization height in the separation areas and the planarization height is substantially equal to the sum of the height of the conductive signal lines and the covering height.

Abstract translation: 柔性电路板的平面化覆盖层结构包括通过第一粘合剂层粘合到布置在柔性电路板的基板上的每个导电信号线的表面的绝缘层。 分别在相邻的导电信号线之间形成的分离区域各自形成有填充层，使得填充层在分离区域中为第一粘合剂层提供平坦化高度，并且平坦化高度基本上等于 导电信号线。 填充层可以替代地具有比导体层的表面高一个覆盖高度的高度，使得第一粘合剂层在分离区域中具有平坦化高度，并且平坦化高度基本上等于高度 的导电信号线和覆盖高度。

公开(公告)号：US08860531B2

公开(公告)日：2014-10-14

申请号：US13444510

申请日：2012-04-11

Applicant: Robert Ziegler

Inventor： Robert Ziegler

IPC: H03H7/075 ,  H03H7/42 ,  H05K1/16 ,  H03H7/01 ,  H03H1/00

CPC classification number: H05K1/162 ,  H03H7/0115 ,  H03H7/42 ,  H03H7/425 ,  H03H2001/0085 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/1006

Abstract: An electrical circuit arrangement provides a substrate and at least two conductive surfaces. The substrate comprises at least one layer disposed between the conductive surfaces. The conductive surfaces form a capacitor and overlap in part and form an overlapping area. In the event of a displacement of the conductive surfaces relative to one another, the resulting overlapping area is largely constant up to a threshold value of the displacement.

Abstract translation: 电路装置提供衬底和至少两个导电表面。 衬底包括设置在导电表面之间的至少一层。 导电表面形成电容器并且部分重叠并形成重叠区域。 在导电表面相对于彼此移位的情况下，所产生的重叠区域大部分恒定直到位移的阈值。