公开(公告)号：US20120211880A9

公开(公告)日：2012-08-23

申请号：US12757889

申请日：2010-04-09

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L23/49838 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.

Abstract translation: 通过将互连凸块配合到引线或迹线上的窄互连焊盘而不是捕获板上，来制造衬底上的管芯的倒装芯片互连。 窄互连焊盘的宽度小于要连接的裸片上的凸块的基底直径。 此外，倒装芯片封装包括具有附着到有源表面中的互连焊盘的焊料凸块的芯片，以及在芯片附着表面中的导电迹线上具有窄互连焊盘的衬底，其中凸块配合到 痕迹

公开(公告)号：US08222530B2

公开(公告)日：2012-07-17

申请号：US12654101

申请日：2009-12-10

Applicant: Saori Ishigaki

Inventor： Saori Ishigaki

IPC: H05K1/00

CPC classification number: H05K1/0269 ,  G11B5/484 ,  G11B5/486 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/225 ,  H05K3/28 ,  H05K2201/0909 ,  H05K2201/09745 ,  H05K2201/09781 ,  H05K2201/0989 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133

Abstract: A wired-circuit-board assembly sheet includes a plurality of wired circuit boards and a supporting sheet for supporting the wired circuit boards in an aligned state. Each of the wired circuit boards includes a distinguishing mark forming portion to be formed with a distinguishing mark for distinguishing between defectiveness and non-defectiveness of the wired circuit board. The distinguishing mark forming portion is divided by a weir portion for preventing the distinguishing mark from flowing out from the distinguishing mark forming portion.

Abstract translation: 布线电路板组装片包括多个布线电路板和用于支撑处于对准状态的布线电路板的支撑片。 每个布线电路板包括一个区别标记形成部分，形成有用于区分布线电路板的缺陷性和非缺陷性的区别标记。 识别标记形成部分被堰部分除以防止区分标记从区分标记形成部分流出。

公开(公告)号：US20120153506A1

公开(公告)日：2012-06-21

申请号：US13329582

申请日：2011-12-19

Applicant: Yoshihiro MACHIDA

Inventor： Yoshihiro MACHIDA

IPC: H01L23/498 ,  H05K1/11 ,  H01L21/56

CPC classification number: H05K3/3452 ,  H01L21/563 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8182 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2924/00013 ,  H05K3/3436 ,  H05K2201/0989 ,  H05K2201/10977 ,  H05K2203/1189 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: A wiring substrate includes a plurality of connection pads, and a protection insulating layer in which opening portion exposing said plurality of connection pads collectively is provided, wherein a notched opening portion is provided to a sidewall of the opening portion of the protection insulating layer in area between said plurality of connection pads. When a semiconductor chip is flip-chip connected to the connection pads by the prior sealing technology, a void occurring in the sealing resin is trapped in the notched opening portion.

Abstract translation: 布线基板包括多个连接焊盘，以及保护绝缘层，其中开放部分共同地露出所述多个连接焊盘，其中在区域中的保护绝缘层的开口部分的侧壁上设有开槽部分 在所述多个连接焊盘之间。 当通过现有的密封技术将半导体芯片倒装芯片连接到连接焊盘时，在密封树脂中发生的空隙被捕获在缺口开口部分中。

公开(公告)号：US20120103664A1

公开(公告)日：2012-05-03

申请号：US13381454

申请日：2010-06-25

Applicant: Ronald Frosch ,  Manfred Riedler

Inventor： Ronald Frosch ,  Manfred Riedler

IPC: H01B7/29

CPC classification number: H05K1/02 ,  H05K1/0298 ,  H05K1/0373 ,  H05K3/3452 ,  H05K2201/012 ,  H05K2201/0209 ,  H05K2201/09309 ,  H05K2201/0989

Abstract: In the case of a multilayered printed circuit board (20), more particularly a flame-resistant and/or smoke-suppressing multilayered printed circuit board, consisting of a plurality of interconnected layers (2, 3, 12, 13) composed of incombustible, conductive material and layers (1, 11) composed of non-conductive material, two layers (2, 3, 12) composed of a conductive material in each case being separated by at least one layer (1, 11) composed of a non-conductive material, it is provided that the printed circuit board (20) contains in its interior at least two layers (2, 3, 12) having a surface proportion of at least 50%, more particularly at last 70%, composed of the incombustible, conductive material, as a result of which a multilayered printed circuit board (20) having improved flame resistance and reduced smoke evolution can be made available.

Abstract translation: 在多层印刷电路板（20）的情况下，更特别地，由多个互不连续的层（2,3,12,13）组成的阻燃和/或防烟多层印刷电路板， 导电材料和由非导电材料构成的层（1,11），由每种情况由导电材料组成的两层（2,3,12）由至少一层由非金属材料构成的层（1,11）隔开， 导电材料，其中印刷电路板（20）在其内部包含至少两层（2,3，12），其表面比例至少为50％，更特别地至少为70％，由不可燃的 导电材料，由此可以获得具有改进的阻燃性和减少的烟雾逸出的多层印刷电路板（20）。

公开(公告)号：US08102659B2

公开(公告)日：2012-01-24

申请号：US10962716

申请日：2004-10-13

Applicant: Yeun-Mo Yeon

Inventor： Yeun-Mo Yeon

IPC: H05K1/00

CPC classification number: H05K1/028 ,  G02F1/13452 ,  H05K3/281 ,  H05K3/361 ,  H05K2201/09063 ,  H05K2201/0989

Abstract: In a flexible printed circuit board and a liquid crystal display, the liquid crystal display includes a flexible printed circuit board electrically connecting a liquid crystal display panel that displays an image and a driving circuit board that outputs a driving signal. The flexible printed circuit board includes a base film, an insulating layer and a signal line disposed between the base film and the insulating layer. The base film or the insulating layer includes an opening formed therethrough. Also, the flexible printed circuit board includes a deformation prevention member by cutting-away an end thereof so as to prevent heat deformation of the flexible printed circuit board. Thus, the liquid crystal display may have reduced size and improved assembly efficiency.

Abstract translation: 在柔性印刷电路板和液晶显示器中，液晶显示器包括电连接显示图像的液晶显示面板和输出驱动信号的驱动电路板的柔性印刷电路板。 柔性印刷电路板包括基膜，绝缘层和设置在基膜和绝缘层之间的信号线。 基膜或绝缘层包括通过其形成的开口。 此外，柔性印刷电路板包括通过切除其端部以防止柔性印刷电路板的热变形的变形防止构件。 因此，液晶显示器可以具有减小的尺寸并提高组装效率。

公开(公告)号：US08049337B2

公开(公告)日：2011-11-01

申请号：US11790030

申请日：2007-04-23

Applicant: Yun-Lung Chang ,  Ming-Wei Sun

Inventor： Yun-Lung Chang ,  Ming-Wei Sun

IPC: H01L23/48

CPC classification number: H05K3/0052 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01033 ,  H05K3/242 ,  H05K3/28 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2201/0989 ,  H05K2203/175 ,  H01L2224/48 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A substrate board and a manufacturing method of a package structure are provided. The substrate board includes a first surface, a die-attaching area, a cutting area, a plurality of first pads and a first solder mask. The die-attaching area for attaching a die is located on the first surface. The first pads are disposed on the first surface. The first solder mask is partially disposed on the first surface to expose part of the cutting area and the first pads. The first solder mask is divided into a first inner area and a first outer area via the cutting area. The die-attaching area and the first pads are located in the first inner area. Wherein, part of the first mask is located on the cutting area for connecting the first inner area and the first outer area.

Abstract translation: 提供了一种基板和一种封装结构的制造方法。 基板包括第一表面，管芯附着区域，切割区域，多个第一焊盘和第一焊接掩模。 用于附接模具的模具附接区域位于第一表面上。 第一焊盘设置在第一表面上。 第一焊接掩模部分地设置在第一表面上以暴露部分切割区域和第一焊盘。 第一焊接掩模经由切割区域分成第一内部区域和第一外部区域。 管芯附着区域和第一焊盘位于第一内部区域中。 其中，第一掩模的一部分位于用于连接第一内部区域和第一外部区域的切割区域上。

公开(公告)号：US20110198760A1

公开(公告)日：2011-08-18

申请号：US12929665

申请日：2011-02-07

Applicant: Koujirou Shibuya

Inventor： Koujirou Shibuya

IPC: H01L23/48 ,  H05K1/11 ,  H01L21/50 ,  H05K3/00

CPC classification number: H05K3/3452 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/0989 ,  H05K2201/10378 ,  Y10T29/49124 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A technique which prevents cracking in a solder resist layer covering an interposer surface between external coupling terminals of an interconnection substrate, thereby reducing the possibility of interconnect wire disconnection resulting from such cracking. A semiconductor package is mounted over an interconnection substrate. An underfill resin layer seals the space between the semiconductor package and the interconnection substrate. External coupling terminals, interconnect wires and a solder resist layer are formed over the surface of an interposer (constituent of the semiconductor package) where the semiconductor chip is not mounted. In an area where an interconnect wire passing between two neighboring ones of the external coupling terminals intersects with a line connecting the centers of the two external coupling terminals, the interconnect wire is not covered by the solder resist layer.

Abstract translation: 防止在互连基板的外部耦合端子之间覆盖介质表面的阻焊层中的开裂的技术，从而减少由于这种开裂导致的互连线断开的可能性。 半导体封装安装在互连衬底上。 底部填充树脂层密封半导体封装和互连衬底之间的空间。 外部耦合端子，互连线和阻焊层形成在半导体芯片未安装的插入件（半导体封装的组成部分）的表面上。 在通过两个相邻的外部耦合端子的互连线与连接两个外部耦合端子的中心的线相交的区域中，互连线不被阻焊层覆盖。

公开(公告)号：US07999190B2

公开(公告)日：2011-08-16

申请号：US12238251

申请日：2008-09-25

Applicant: Sadamichi Takakusaki ,  Koichiro Ono ,  Akihisa Matsumoto

Inventor： Sadamichi Takakusaki ,  Koichiro Ono ,  Akihisa Matsumoto

IPC: H05K1/16

CPC classification number: H05K1/056 ,  H01L33/486 ,  H01L33/62 ,  H01L33/64 ,  H01L2224/48465 ,  H01L2224/73265 ,  H05K3/002 ,  H05K3/0032 ,  H05K2201/0989 ,  H05K2201/10106 ,  Y10T29/49169 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: Provided are: a light emitting module which has an improved heat-dissipating property and whose reflectance reduction is prevented. The light emitting module mainly includes: a metal substrate; a conductive pattern formed on the upper surface of the metal substrate; and a light emitting element disposed on the upper surface of the metal substrate and electrically connected to the conductive pattern. Furthermore, in the light emitting module, an insulating layer is removed in a region where the conductive pattern is not formed, but is left unremoved in a region right below (or covered with) the conductive pattern. In other words, in the region where the conductive pattern is not formed, the upper surface of the metal substrate is not covered with the conductive pattern, and a metal material constituting the metal substrate is exposed.

Abstract translation: 提供：具有改善的散热特性并防止其反射率降低的发光模块。 发光模块主要包括：金属基板; 形成在所述金属基板的上表面上的导电图案; 以及设置在金属基板的上表面并电连接到导电图案的发光元件。 此外，在发光模块中，在未形成导电图案的区域中去除绝缘层，但在导电图案的正下方（或被覆盖）的区域中不会去除绝缘层。 换句话说，在未形成导电图案的区域中，金属基板的上表面不被导电图案覆盖，并且构成金属基板的金属材料露出。

公开(公告)号：US20110169121A1

公开(公告)日：2011-07-14

申请号：US12952173

申请日：2010-11-22

Applicant: Peter Steven Bui ,  Narayan Dass Taneja

Inventor： Peter Steven Bui ,  Narayan Dass Taneja

IPC: H01L31/0216

CPC classification number: H01L27/14643 ,  B23K1/0016 ,  B23K2101/42 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14692 ,  H05K3/26 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10689 ,  H05K2201/10727

Abstract: The present invention is directed toward a detector structure, detector arrays, and a method of detecting incident radiation. The present invention comprises several embodiments that provide for reduced radiation damage susceptibility, decreased affects of crosstalk, reduced dark current (current leakage) and increased flexibility in application. In one embodiment, a photodiode array comprises a substrate having at least a front side and a back side, a plurality of diode elements integrally formed in the substrate forming the array, wherein each diode element has a p+ fishbone pattern on the front side, and wherein the p+ fishbone pattern substantially reduces capacitance and crosstalk between adjacent photodiodes, a plurality of front surface cathode and anode contacts, and wire interconnects between diode elements made through a plurality of back surface contacts.

Abstract translation: 本发明涉及检测器结构，检测器阵列和检测入射辐射的方法。 本发明包括几个实施例，其提供减少的辐射损伤敏感性，降低的串扰影响，降低的暗电流（电流泄漏）和增加的应用灵活性。 在一个实施例中，光电二极管阵列包括至少具有前侧和背面的基板，在形成阵列的基板中一体形成的多个二极管元件，其中每个二极管元件在前侧具有p +鱼骨图案，以及 其中所述p +鱼骨图案基本上减小了相邻光电二极管之间的电容和串扰，多个前表面阴极和阳极触点以及通过多个后表面触点制成的二极管元件之间的导线互连。

公开(公告)号：US07957151B2

公开(公告)日：2011-06-07

申请号：US12063152

申请日：2006-10-30

Applicant: Tetsuya Aita ,  Yoshimasa Chikama

Inventor： Tetsuya Aita ,  Yoshimasa Chikama

IPC: H05K1/00

CPC classification number: H05K3/323 ,  G02F1/13452 ,  H01L24/16 ,  H01L24/83 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H05K3/3452 ,  H05K3/386 ,  H05K3/388 ,  H05K2201/0179 ,  H05K2201/0989 ,  H05K2201/10674 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/05599

Abstract: An electrode connection structure including a first circuit component including a resin plate, a barrier film stacked on a surface of the resin plate, a circuit section formed on the barrier film and a first electrode provided on the surface of the resin plate on which the barrier film is stacked, and a second circuit component arranged to face the first circuit component and having a second electrode facing the first electrode, wherein the first and second electrodes are electrically connected via pressure applied thereto in the directions approaching each other and a portion of the barrier film surrounding the first electrode is at least partially removed from the surface of the resin plate.

Abstract translation: 一种电极连接结构，包括：第一电路部件，包括树脂板，层叠在树脂板的表面上的阻挡膜，形成在阻挡膜上的电路部分和设置在树脂板的表面上的第一电极， 并且第二电路部件布置成面向第一电路部件并且具有面向第一电极的第二电极，其中第一和第二电极经由施加到其上的压力在彼此接近的方向上电连接，并且部分 围绕第一电极的阻挡膜至少部分地从树脂板的表面去除。